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https://github.com/c64scene-ar/llvm-6502.git
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c0e669384d
Patch by Yuri Gorshenin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209280 91177308-0d34-0410-b5e6-96231b3b80d8
255 lines
8.6 KiB
C++
255 lines
8.6 KiB
C++
//===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86AsmInstrumentation.h"
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#include "X86Operand.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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namespace llvm {
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namespace {
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static cl::opt<bool> ClAsanInstrumentAssembly(
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"asan-instrument-assembly",
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cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
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cl::init(false));
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bool IsStackReg(unsigned Reg) {
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return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
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}
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std::string FuncName(unsigned AccessSize, bool IsWrite) {
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return std::string("__sanitizer_sanitize_") + (IsWrite ? "store" : "load") +
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(utostr(AccessSize));
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}
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class X86AddressSanitizer : public X86AsmInstrumentation {
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public:
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X86AddressSanitizer(const MCSubtargetInfo &STI) : STI(STI) {}
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virtual ~X86AddressSanitizer() {}
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// X86AsmInstrumentation implementation:
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virtual void InstrumentInstruction(
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const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) override {
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InstrumentMOV(Inst, Operands, Ctx, MII, Out);
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}
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// Should be implemented differently in x86_32 and x86_64 subclasses.
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virtual void InstrumentMemOperandImpl(X86Operand *Op, unsigned AccessSize,
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bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) = 0;
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void InstrumentMemOperand(MCParsedAsmOperand *Op, unsigned AccessSize,
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bool IsWrite, MCContext &Ctx, MCStreamer &Out);
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void InstrumentMOV(const MCInst &Inst,
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SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
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void EmitInstruction(MCStreamer &Out, const MCInst &Inst) {
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Out.EmitInstruction(Inst, STI);
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}
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protected:
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const MCSubtargetInfo &STI;
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};
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void X86AddressSanitizer::InstrumentMemOperand(
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MCParsedAsmOperand *Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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assert(Op && Op->isMem() && "Op should be a memory operand.");
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assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
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"AccessSize should be a power of two, less or equal than 16.");
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X86Operand *MemOp = static_cast<X86Operand *>(Op);
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// FIXME: get rid of this limitation.
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if (IsStackReg(MemOp->getMemBaseReg()) || IsStackReg(MemOp->getMemIndexReg()))
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return;
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InstrumentMemOperandImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOV(
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const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) {
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// Access size in bytes.
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unsigned AccessSize = 0;
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switch (Inst.getOpcode()) {
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case X86::MOV8mi:
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case X86::MOV8mr:
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case X86::MOV8rm:
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AccessSize = 1;
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break;
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case X86::MOV16mi:
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case X86::MOV16mr:
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case X86::MOV16rm:
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AccessSize = 2;
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break;
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case X86::MOV32mi:
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case X86::MOV32mr:
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case X86::MOV32rm:
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AccessSize = 4;
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break;
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case X86::MOV64mi32:
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case X86::MOV64mr:
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case X86::MOV64rm:
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AccessSize = 8;
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break;
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case X86::MOVAPDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDrm:
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case X86::MOVAPSrm:
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AccessSize = 16;
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break;
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default:
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return;
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}
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const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
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for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
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MCParsedAsmOperand *Op = Operands[Ix];
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if (Op && Op->isMem())
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InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
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}
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}
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class X86AddressSanitizer32 : public X86AddressSanitizer {
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public:
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X86AddressSanitizer32(const MCSubtargetInfo &STI)
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: X86AddressSanitizer(STI) {}
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virtual ~X86AddressSanitizer32() {}
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virtual void InstrumentMemOperandImpl(X86Operand *Op, unsigned AccessSize,
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bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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};
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void X86AddressSanitizer32::InstrumentMemOperandImpl(
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X86Operand *Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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// FIXME: emit .cfi directives for correct stack unwinding.
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::EAX));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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{
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const std::string Func = FuncName(AccessSize, IsWrite);
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const MCSymbol *FuncSym = Ctx.GetOrCreateSymbol(StringRef(Func));
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const MCSymbolRefExpr *FuncExpr =
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MCSymbolRefExpr::Create(FuncSym, MCSymbolRefExpr::VK_PLT, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FuncExpr));
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}
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
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}
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class X86AddressSanitizer64 : public X86AddressSanitizer {
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public:
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X86AddressSanitizer64(const MCSubtargetInfo &STI)
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: X86AddressSanitizer(STI) {}
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virtual ~X86AddressSanitizer64() {}
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virtual void InstrumentMemOperandImpl(X86Operand *Op, unsigned AccessSize,
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bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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};
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void X86AddressSanitizer64::InstrumentMemOperandImpl(X86Operand *Op,
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unsigned AccessSize,
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bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) {
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// FIXME: emit .cfi directives for correct stack unwinding.
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// Set %rsp below current red zone (128 bytes wide) using LEA instruction to
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// preserve flags.
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA64r);
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Inst.addOperand(MCOperand::CreateReg(X86::RSP));
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const MCExpr *Disp = MCConstantExpr::Create(-128, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RDI));
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA64r);
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Inst.addOperand(MCOperand::CreateReg(X86::RDI));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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{
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const std::string Func = FuncName(AccessSize, IsWrite);
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const MCSymbol *FuncSym = Ctx.GetOrCreateSymbol(StringRef(Func));
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const MCSymbolRefExpr *FuncExpr =
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MCSymbolRefExpr::Create(FuncSym, MCSymbolRefExpr::VK_PLT, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FuncExpr));
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}
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EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RDI));
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// Restore old %rsp value.
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA64r);
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Inst.addOperand(MCOperand::CreateReg(X86::RSP));
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const MCExpr *Disp = MCConstantExpr::Create(128, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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}
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} // End anonymous namespace
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X86AsmInstrumentation::X86AsmInstrumentation() {}
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X86AsmInstrumentation::~X86AsmInstrumentation() {}
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void X86AsmInstrumentation::InstrumentInstruction(
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const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) {}
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X86AsmInstrumentation *
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CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
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const MCContext &Ctx, const MCSubtargetInfo &STI) {
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Triple T(STI.getTargetTriple());
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const bool hasCompilerRTSupport = T.isOSLinux();
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if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
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MCOptions.SanitizeAddress) {
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if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
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return new X86AddressSanitizer32(STI);
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if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
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return new X86AddressSanitizer64(STI);
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}
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return new X86AsmInstrumentation();
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}
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} // End llvm namespace
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