llvm-6502/test/MC/Disassembler
2014-03-02 21:17:44 +00:00
..
AArch64
ARM ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions 2014-01-12 04:36:01 +00:00
Mips LL and SC decoder method fix. 2014-01-15 13:17:33 +00:00
PowerPC Add a disassembler to the PowerPC backend 2013-12-19 16:13:01 +00:00
Sparc [Sparc] Add support for decoding jmpl/retl/ret instruction. 2014-03-02 21:17:44 +00:00
SystemZ [SystemZ] Add MC support for interlocked-access 1 instructions 2013-12-24 15:14:05 +00:00
X86 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 2014-02-19 05:34:21 +00:00
XCore