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D0<def,dead> = ... ... = S0<use, kill> S0<def> = ... ... D0<def> = The first D0 def is correctly marked dead, however, livevariables should have added an implicit def of S0 or we end up with a use without a def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88690 91177308-0d34-0410-b5e6-96231b3b80d8
691 lines
25 KiB
C++
691 lines
25 KiB
C++
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveVariable analysis pass. For each machine
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// instruction in the function, this pass calculates the set of registers that
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// are immediately dead after the instruction (i.e., the instruction calculates
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// the value, but it is never used) and the set of registers that are used by
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// the instruction, but are never used after the instruction (i.e., they are
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// killed).
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//
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// This class computes live variables using are sparse implementation based on
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// the machine code SSA form. This class computes live variable information for
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// each virtual and _register allocatable_ physical register in a function. It
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// uses the dominance properties of SSA form to efficiently compute live
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// variables for virtual registers, and assumes that physical registers are only
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// live within a single basic block (allowing it to do a single local analysis
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// to resolve physical register lifetimes in each basic block). If a physical
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// register is not register allocatable, it is not tracked. This is useful for
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// things like the stack pointer and condition codes.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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using namespace llvm;
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char LiveVariables::ID = 0;
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static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
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void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequiredID(UnreachableMachineBlockElimID);
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineInstr *
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LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
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for (unsigned i = 0, e = Kills.size(); i != e; ++i)
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if (Kills[i]->getParent() == MBB)
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return Kills[i];
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return NULL;
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}
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void LiveVariables::VarInfo::dump() const {
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errs() << " Alive in blocks: ";
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for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
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E = AliveBlocks.end(); I != E; ++I)
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errs() << *I << ", ";
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errs() << "\n Killed by:";
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if (Kills.empty())
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errs() << " No instructions.\n";
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else {
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for (unsigned i = 0, e = Kills.size(); i != e; ++i)
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errs() << "\n #" << i << ": " << *Kills[i];
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errs() << "\n";
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}
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}
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/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
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LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
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assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
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"getVarInfo: not a virtual register!");
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RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
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if (RegIdx >= VirtRegInfo.size()) {
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if (RegIdx >= 2*VirtRegInfo.size())
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VirtRegInfo.resize(RegIdx*2);
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else
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VirtRegInfo.resize(2*VirtRegInfo.size());
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}
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return VirtRegInfo[RegIdx];
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
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MachineBasicBlock *DefBlock,
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MachineBasicBlock *MBB,
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std::vector<MachineBasicBlock*> &WorkList) {
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unsigned BBNum = MBB->getNumber();
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// Check to see if this basic block is one of the killing blocks. If so,
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// remove it.
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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if (VRInfo.Kills[i]->getParent() == MBB) {
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VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
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break;
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}
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if (MBB == DefBlock) return; // Terminate recursion
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if (VRInfo.AliveBlocks.test(BBNum))
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return; // We already know the block is live
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// Mark the variable known alive in this bb
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VRInfo.AliveBlocks.set(BBNum);
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for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
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E = MBB->pred_rend(); PI != E; ++PI)
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WorkList.push_back(*PI);
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
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MachineBasicBlock *DefBlock,
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MachineBasicBlock *MBB) {
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std::vector<MachineBasicBlock*> WorkList;
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
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while (!WorkList.empty()) {
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MachineBasicBlock *Pred = WorkList.back();
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WorkList.pop_back();
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
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}
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}
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void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
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MachineInstr *MI) {
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assert(MRI->getVRegDef(reg) && "Register use before def!");
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unsigned BBNum = MBB->getNumber();
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VarInfo& VRInfo = getVarInfo(reg);
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VRInfo.NumUses++;
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// Check to see if this basic block is already a kill block.
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if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
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// Yes, this register is killed in this basic block already. Increase the
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// live range by updating the kill instruction.
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VRInfo.Kills.back() = MI;
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return;
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}
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#ifndef NDEBUG
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
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#endif
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// This situation can occur:
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//
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// ,------.
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// | |
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// | v
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// | t2 = phi ... t1 ...
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// | |
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// | v
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// | t1 = ...
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// | ... = ... t1 ...
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// | |
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// `------'
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//
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// where there is a use in a PHI node that's a predecessor to the defining
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// block. We don't want to mark all predecessors as having the value "alive"
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// in this case.
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if (MBB == MRI->getVRegDef(reg)->getParent()) return;
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// Add a new kill entry for this basic block. If this virtual register is
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// already marked as alive in this basic block, that means it is alive in at
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// least one of the successor blocks, it's not a kill.
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if (!VRInfo.AliveBlocks.test(BBNum))
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VRInfo.Kills.push_back(MI);
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// Update all dominating blocks to mark them as "known live".
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for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
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E = MBB->pred_end(); PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
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}
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void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
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VarInfo &VRInfo = getVarInfo(Reg);
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if (VRInfo.AliveBlocks.empty())
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// If vr is not alive in any block, then defaults to dead.
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VRInfo.Kills.push_back(MI);
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}
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/// FindLastPartialDef - Return the last partial def of the specified register.
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/// Also returns the sub-registers that're defined by the instruction.
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MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
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SmallSet<unsigned,4> &PartDefRegs) {
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unsigned LastDefReg = 0;
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unsigned LastDefDist = 0;
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MachineInstr *LastDef = NULL;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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MachineInstr *Def = PhysRegDef[SubReg];
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if (!Def)
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continue;
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unsigned Dist = DistanceMap[Def];
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if (Dist > LastDefDist) {
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LastDefReg = SubReg;
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LastDef = Def;
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LastDefDist = Dist;
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}
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}
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if (!LastDef)
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return 0;
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PartDefRegs.insert(LastDefReg);
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for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = LastDef->getOperand(i);
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if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
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continue;
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unsigned DefReg = MO.getReg();
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if (TRI->isSubRegister(Reg, DefReg)) {
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PartDefRegs.insert(DefReg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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PartDefRegs.insert(SubReg);
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}
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}
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return LastDef;
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}
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/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
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/// implicit defs to a machine instruction if there was an earlier def of its
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/// super-register.
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void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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MachineInstr *LastDef = PhysRegDef[Reg];
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// If there was a previous use or a "full" def all is well.
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if (!LastDef && !PhysRegUse[Reg]) {
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// Otherwise, the last sub-register def implicitly defines this register.
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// e.g.
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// AH =
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// AL = ... <imp-def EAX>, <imp-kill AH>
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// = AH
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// ...
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// = EAX
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// All of the sub-registers must have been defined before the use of Reg!
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SmallSet<unsigned, 4> PartDefRegs;
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MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
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// If LastPartialDef is NULL, it must be using a livein register.
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if (LastPartialDef) {
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LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
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true/*IsImp*/));
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PhysRegDef[Reg] = LastPartialDef;
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SmallSet<unsigned, 8> Processed;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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if (Processed.count(SubReg))
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continue;
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if (PartDefRegs.count(SubReg))
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continue;
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// This part of Reg was defined before the last partial def. It's killed
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// here.
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LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
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false/*IsDef*/,
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true/*IsImp*/));
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PhysRegDef[SubReg] = LastPartialDef;
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for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
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Processed.insert(*SS);
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}
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}
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}
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else if (LastDef && !PhysRegUse[Reg] &&
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!LastDef->findRegisterDefOperand(Reg))
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// Last def defines the super register, add an implicit def of reg.
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LastDef->addOperand(MachineOperand::CreateReg(Reg,
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true/*IsDef*/, true/*IsImp*/));
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// Remember this use.
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PhysRegUse[Reg] = MI;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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PhysRegUse[SubReg] = MI;
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}
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bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
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MachineInstr *LastDef = PhysRegDef[Reg];
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MachineInstr *LastUse = PhysRegUse[Reg];
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if (!LastDef && !LastUse)
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return false;
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MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
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unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
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// The whole register is used.
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// AL =
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// AH =
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//
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// = AX
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// = AL, AX<imp-use, kill>
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// AX =
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//
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// Or whole register is defined, but not used at all.
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// AX<dead> =
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// ...
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// AX =
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//
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// Or whole register is defined, but only partly used.
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// AX<dead> = AL<imp-def>
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// = AL<kill>
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// AX =
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MachineInstr *LastPartDef = 0;
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unsigned LastPartDefDist = 0;
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SmallSet<unsigned, 8> PartUses;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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MachineInstr *Def = PhysRegDef[SubReg];
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if (Def && Def != LastDef) {
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// There was a def of this sub-register in between. This is a partial
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// def, keep track of the last one.
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unsigned Dist = DistanceMap[Def];
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if (Dist > LastPartDefDist) {
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LastPartDefDist = Dist;
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LastPartDef = Def;
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}
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continue;
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}
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if (MachineInstr *Use = PhysRegUse[SubReg]) {
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PartUses.insert(SubReg);
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for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
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PartUses.insert(*SS);
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unsigned Dist = DistanceMap[Use];
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if (Dist > LastRefOrPartRefDist) {
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LastRefOrPartRefDist = Dist;
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LastRefOrPartRef = Use;
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}
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}
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}
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if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
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if (LastPartDef)
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// The last partial def kills the register.
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LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
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true/*IsImp*/, true/*IsKill*/));
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else {
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MachineOperand *MO =
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LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
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bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
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// If the last reference is the last def, then it's not used at all.
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// That is, unless we are currently processing the last reference itself.
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LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
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if (NeedEC) {
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// If we are adding a subreg def and the superreg def is marked early
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// clobber, add an early clobber marker to the subreg def.
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MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
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if (MO)
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MO->setIsEarlyClobber();
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}
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}
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} else if (!PhysRegUse[Reg]) {
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// Partial uses. Mark register def dead and add implicit def of
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// sub-registers which are used.
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// EAX<dead> = op AL<imp-def>
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// That is, EAX def is dead but AL def extends pass it.
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PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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if (!PartUses.count(SubReg))
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continue;
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bool NeedDef = true;
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if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
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MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
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if (MO) {
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NeedDef = false;
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assert(!MO->isDead());
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}
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}
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if (NeedDef)
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PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
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true/*IsDef*/, true/*IsImp*/));
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LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
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for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
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PartUses.erase(*SS);
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}
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} else
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LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
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return true;
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}
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
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SmallVector<unsigned, 4> &Defs) {
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// What parts of the register are previously defined?
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SmallSet<unsigned, 32> Live;
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if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
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Live.insert(Reg);
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for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
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Live.insert(*SS);
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} else {
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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// If a register isn't itself defined, but all parts that make up of it
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// are defined, then consider it also defined.
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// e.g.
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// AL =
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// AH =
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// = AX
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if (Live.count(SubReg))
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continue;
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if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
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Live.insert(SubReg);
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for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
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Live.insert(*SS);
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}
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}
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}
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// Start from the largest piece, find the last time any part of the register
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// is referenced.
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HandlePhysRegKill(Reg, MI);
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// Only some of the sub-registers are used.
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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if (!Live.count(SubReg))
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// Skip if this sub-register isn't defined.
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continue;
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HandlePhysRegKill(SubReg, MI);
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}
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if (MI)
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Defs.push_back(Reg); // Remember this def.
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}
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void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
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SmallVector<unsigned, 4> &Defs) {
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while (!Defs.empty()) {
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unsigned Reg = Defs.back();
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Defs.pop_back();
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PhysRegDef[Reg] = MI;
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PhysRegUse[Reg] = NULL;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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PhysRegDef[SubReg] = MI;
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PhysRegUse[SubReg] = NULL;
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}
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}
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}
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namespace {
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struct RegSorter {
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const TargetRegisterInfo *TRI;
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RegSorter(const TargetRegisterInfo *tri) : TRI(tri) { }
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bool operator()(unsigned A, unsigned B) {
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if (TRI->isSubRegister(A, B))
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return true;
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else if (TRI->isSubRegister(B, A))
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return false;
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return A < B;
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}
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};
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}
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bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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MRI = &mf.getRegInfo();
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TRI = MF->getTarget().getRegisterInfo();
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ReservedRegisters = TRI->getReservedRegs(mf);
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unsigned NumRegs = TRI->getNumRegs();
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PhysRegDef = new MachineInstr*[NumRegs];
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PhysRegUse = new MachineInstr*[NumRegs];
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PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
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std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
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std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
|
|
|
|
/// Get some space for a respectable number of registers.
|
|
VirtRegInfo.resize(64);
|
|
|
|
analyzePHINodes(mf);
|
|
|
|
// Calculate live variable information in depth first order on the CFG of the
|
|
// function. This guarantees that we will see the definition of a virtual
|
|
// register before its uses due to dominance properties of SSA (except for PHI
|
|
// nodes, which are treated as a special case).
|
|
MachineBasicBlock *Entry = MF->begin();
|
|
SmallPtrSet<MachineBasicBlock*,16> Visited;
|
|
|
|
for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
|
|
DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
|
|
DFI != E; ++DFI) {
|
|
MachineBasicBlock *MBB = *DFI;
|
|
|
|
// Mark live-in registers as live-in.
|
|
SmallVector<unsigned, 4> Defs;
|
|
for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
|
|
EE = MBB->livein_end(); II != EE; ++II) {
|
|
assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
|
|
"Cannot have a live-in virtual register!");
|
|
HandlePhysRegDef(*II, 0, Defs);
|
|
}
|
|
|
|
// Loop over all of the instructions, processing them.
|
|
DistanceMap.clear();
|
|
unsigned Dist = 0;
|
|
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
|
|
I != E; ++I) {
|
|
MachineInstr *MI = I;
|
|
DistanceMap.insert(std::make_pair(MI, Dist++));
|
|
|
|
// Process all of the operands of the instruction...
|
|
unsigned NumOperandsToProcess = MI->getNumOperands();
|
|
|
|
// Unless it is a PHI node. In this case, ONLY process the DEF, not any
|
|
// of the uses. They will be handled in other basic blocks.
|
|
if (MI->getOpcode() == TargetInstrInfo::PHI)
|
|
NumOperandsToProcess = 1;
|
|
|
|
SmallVector<unsigned, 4> UseRegs;
|
|
SmallVector<unsigned, 4> DefRegs;
|
|
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || MO.getReg() == 0)
|
|
continue;
|
|
unsigned MOReg = MO.getReg();
|
|
if (MO.isUse())
|
|
UseRegs.push_back(MOReg);
|
|
if (MO.isDef())
|
|
DefRegs.push_back(MOReg);
|
|
}
|
|
|
|
// Process all uses.
|
|
for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
|
|
unsigned MOReg = UseRegs[i];
|
|
if (TargetRegisterInfo::isVirtualRegister(MOReg))
|
|
HandleVirtRegUse(MOReg, MBB, MI);
|
|
else if (!ReservedRegisters[MOReg])
|
|
HandlePhysRegUse(MOReg, MI);
|
|
}
|
|
|
|
// Process all defs.
|
|
for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
|
|
unsigned MOReg = DefRegs[i];
|
|
if (TargetRegisterInfo::isVirtualRegister(MOReg))
|
|
HandleVirtRegDef(MOReg, MI);
|
|
else if (!ReservedRegisters[MOReg])
|
|
HandlePhysRegDef(MOReg, MI, Defs);
|
|
}
|
|
UpdatePhysRegDefs(MI, Defs);
|
|
}
|
|
|
|
// Handle any virtual assignments from PHI nodes which might be at the
|
|
// bottom of this basic block. We check all of our successor blocks to see
|
|
// if they have PHI nodes, and if so, we simulate an assignment at the end
|
|
// of the current block.
|
|
if (!PHIVarInfo[MBB->getNumber()].empty()) {
|
|
SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
|
|
|
|
for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
|
|
E = VarInfoVec.end(); I != E; ++I)
|
|
// Mark it alive only in the block we are representing.
|
|
MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
|
|
MBB);
|
|
}
|
|
|
|
// Finally, if the last instruction in the block is a return, make sure to
|
|
// mark it as using all of the live-out values in the function.
|
|
if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
|
|
MachineInstr *Ret = &MBB->back();
|
|
|
|
for (MachineRegisterInfo::liveout_iterator
|
|
I = MF->getRegInfo().liveout_begin(),
|
|
E = MF->getRegInfo().liveout_end(); I != E; ++I) {
|
|
assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
|
|
"Cannot have a live-out virtual register!");
|
|
HandlePhysRegUse(*I, Ret);
|
|
|
|
// Add live-out registers as implicit uses.
|
|
if (!Ret->readsRegister(*I))
|
|
Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
|
|
}
|
|
}
|
|
|
|
// Loop over PhysRegDef / PhysRegUse, killing any registers that are
|
|
// available at the end of the basic block.
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
|
if (PhysRegDef[i] || PhysRegUse[i])
|
|
HandlePhysRegDef(i, 0, Defs);
|
|
|
|
std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
|
|
std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
|
|
}
|
|
|
|
// Convert and transfer the dead / killed information we have gathered into
|
|
// VirtRegInfo onto MI's.
|
|
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
|
|
for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
|
|
if (VirtRegInfo[i].Kills[j] ==
|
|
MRI->getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
|
|
VirtRegInfo[i]
|
|
.Kills[j]->addRegisterDead(i +
|
|
TargetRegisterInfo::FirstVirtualRegister,
|
|
TRI);
|
|
else
|
|
VirtRegInfo[i]
|
|
.Kills[j]->addRegisterKilled(i +
|
|
TargetRegisterInfo::FirstVirtualRegister,
|
|
TRI);
|
|
|
|
// Check to make sure there are no unreachable blocks in the MC CFG for the
|
|
// function. If so, it is due to a bug in the instruction selector or some
|
|
// other part of the code generator if this happens.
|
|
#ifndef NDEBUG
|
|
for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
|
|
assert(Visited.count(&*i) != 0 && "unreachable basic block found");
|
|
#endif
|
|
|
|
delete[] PhysRegDef;
|
|
delete[] PhysRegUse;
|
|
delete[] PHIVarInfo;
|
|
|
|
return false;
|
|
}
|
|
|
|
/// replaceKillInstruction - Update register kill info by replacing a kill
|
|
/// instruction with a new one.
|
|
void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
|
|
MachineInstr *NewMI) {
|
|
VarInfo &VI = getVarInfo(Reg);
|
|
std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
|
|
}
|
|
|
|
/// removeVirtualRegistersKilled - Remove all killed info for the specified
|
|
/// instruction.
|
|
void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isReg() && MO.isKill()) {
|
|
MO.setIsKill(false);
|
|
unsigned Reg = MO.getReg();
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
bool removed = getVarInfo(Reg).removeKill(MI);
|
|
assert(removed && "kill not in register's VarInfo?");
|
|
removed = true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// analyzePHINodes - Gather information about the PHI nodes in here. In
|
|
/// particular, we want to map the variable information of a virtual register
|
|
/// which is used in a PHI node. We map that to the BB the vreg is coming from.
|
|
///
|
|
void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
|
|
for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
|
|
I != E; ++I)
|
|
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
|
|
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
|
|
PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
|
|
.push_back(BBI->getOperand(i).getReg());
|
|
}
|
|
|
|
/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
|
|
/// variables that are live out of DomBB will be marked as passing live through
|
|
/// BB.
|
|
void LiveVariables::addNewBlock(MachineBasicBlock *BB,
|
|
MachineBasicBlock *DomBB) {
|
|
const unsigned NumNew = BB->getNumber();
|
|
const unsigned NumDom = DomBB->getNumber();
|
|
|
|
// Update info for all live variables
|
|
for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
|
|
E = MRI->getLastVirtReg()+1; Reg != E; ++Reg) {
|
|
VarInfo &VI = getVarInfo(Reg);
|
|
|
|
// Anything live through DomBB is also live through BB.
|
|
if (VI.AliveBlocks.test(NumDom)) {
|
|
VI.AliveBlocks.set(NumNew);
|
|
continue;
|
|
}
|
|
|
|
// Variables not defined in DomBB cannot be live out.
|
|
const MachineInstr *Def = MRI->getVRegDef(Reg);
|
|
if (!Def || Def->getParent() != DomBB)
|
|
continue;
|
|
|
|
// Killed by DomBB?
|
|
if (VI.findKill(DomBB))
|
|
continue;
|
|
|
|
// This register is defined in DomBB and live out
|
|
VI.AliveBlocks.set(NumNew);
|
|
}
|
|
}
|