mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-18 12:29:27 +00:00
c4ce73f666
It is missing validity checks, so it is known broken. However, it is powerful enough
to compile this contrived code:
void test1(int C, double A, double B, double *P) {
double Tmp = A*A+B*B;
*P = C ? Tmp : A;
}
into:
_test1:
movsd 8(%esp), %xmm0
cmpl $0, 4(%esp)
je LBB1_2 # entry
LBB1_1: # entry
movsd 16(%esp), %xmm1
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
LBB1_2: # entry
movl 24(%esp), %eax
movsd %xmm0, (%eax)
ret
instead of:
_test1:
movsd 16(%esp), %xmm0
mulsd %xmm0, %xmm0
movsd 8(%esp), %xmm1
movapd %xmm1, %xmm2
mulsd %xmm2, %xmm2
addsd %xmm0, %xmm2
cmpl $0, 4(%esp)
je LBB1_2 # entry
LBB1_1: # entry
movapd %xmm2, %xmm1
LBB1_2: # entry
movl 24(%esp), %eax
movsd %xmm1, (%eax)
ret
woo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45570 91177308-0d34-0410-b5e6-96231b3b80d8
231 lines
7.6 KiB
C++
231 lines
7.6 KiB
C++
//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LLVMTargetMachine class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Pass.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/Analysis/LoopPass.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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cl::desc("Print LLVM IR input to isel pass"));
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static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
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cl::desc("Dump emitter generated instructions as assembly"));
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// Hidden options to help debugging
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static cl::opt<bool>
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EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
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cl::desc("Perform sinking on machine code"));
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FileModel::Model
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LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
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std::ostream &Out,
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CodeGenFileType FileType,
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bool Fast) {
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// Standard LLVM-Level Passes.
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// Run loop strength reduction before anything else.
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if (!Fast) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
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}
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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if (!ExceptionHandling)
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PM.add(createLowerInvokePass(getTargetLowering()));
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (!Fast)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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if (PrintISelInput)
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PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
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&cerr));
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// Ask the target for an isel.
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if (addInstSelector(PM, Fast))
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return FileModel::Error;
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// Print the instruction selected machine code...
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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PM.add(createMachineLICMPass());
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if (EnableSinking)
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PM.add(createMachineSinkingPass());
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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PM.add(createLowerSubregsPass());
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if (PrintMachineCode) // Print the subreg lowered code
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Run post-ra passes.
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if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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// Second pass scheduler.
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if (!Fast)
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PM.add(createPostRAScheduler());
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (!Fast)
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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// Fold redundant debug labels.
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PM.add(createDebugLabelFoldingPass());
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if (PrintMachineCode) // Print the register-allocated code
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PM.add(createMachineFunctionPrinterPass(cerr));
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if (addPreEmitPass(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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switch (FileType) {
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default:
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break;
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case TargetMachine::AssemblyFile:
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if (addAssemblyEmitter(PM, Fast, Out))
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return FileModel::Error;
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return FileModel::AsmFile;
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case TargetMachine::ObjectFile:
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if (getMachOWriterInfo())
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return FileModel::MachOFile;
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else if (getELFWriterInfo())
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return FileModel::ElfFile;
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}
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return FileModel::Error;
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}
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/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
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/// be split up (e.g., to add an object writer pass), this method can be used to
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/// finish up adding passes to emit the file, if necessary.
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bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM,
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MachineCodeEmitter *MCE,
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bool Fast) {
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if (MCE)
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addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
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// Delete machine code for this function
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PM.add(createMachineCodeDeleter());
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return false; // success!
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a MachineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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MachineCodeEmitter &MCE,
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bool Fast) {
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// Standard LLVM-Level Passes.
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// Run loop strength reduction before anything else.
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if (!Fast) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
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}
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass(getTargetLowering()));
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (!Fast)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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if (PrintISelInput)
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PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
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&cerr));
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// Ask the target for an isel.
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if (addInstSelector(PM, Fast))
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return true;
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// Print the instruction selected machine code...
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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PM.add(createMachineLICMPass());
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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PM.add(createLowerSubregsPass());
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if (PrintMachineCode) // Print the subreg lowered code
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Run post-ra passes.
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if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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if (PrintMachineCode) // Print the register-allocated code
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Second pass scheduler.
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if (!Fast)
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PM.add(createPostRAScheduler());
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (!Fast)
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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if (addPreEmitPass(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
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// Delete machine code for this function
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PM.add(createMachineCodeDeleter());
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return false; // success!
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}
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