Nadav Rotem 9f40cb32ac Not all targets have efficient ISel code generation for select instructions. ... For example, the ARM target does not have efficient ISel handling for vector selects with scalar conditions. This patch adds a TLI hook which allows the different targets to report which selects are supported well and which selects should be converted to CF duting codegen prepare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163093 91177308-0d34-0410-b5e6-96231b3b80d8		2012-09-02 12:10:19 +00:00
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Mangler.h
Target.td	Tristate mayLoad, mayStore, and hasSideEffects.	2012-08-23 19:34:46 +00:00
TargetCallingConv.h	Convert comments to proper Doxygen comments.	2012-06-09 00:01:45 +00:00
TargetCallingConv.td
TargetData.h	Revert r161371. Removing the 'const' before Type is a "good thing".	2012-08-07 05:51:59 +00:00
TargetELFWriterInfo.h	[Hexagon] Clean up Hexagon ELF definition.	2012-05-17 16:46:46 +00:00
TargetFrameLowering.h
TargetInstrInfo.h	Add a bit of documentation to copyPhysReg.	2012-08-29 23:52:55 +00:00
TargetIntrinsicInfo.h
TargetItinerary.td	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
TargetJITInfo.h
TargetLibraryInfo.h	Make MemoryBuiltins aware of TargetLibraryInfo.	2012-08-29 15:32:21 +00:00
TargetLowering.h	Not all targets have efficient ISel code generation for select instructions.	2012-09-02 12:10:19 +00:00
TargetLoweringObjectFile.h
TargetMachine.h	Extend TargetPassConfig to allow running only a subset of the normal passes.	2012-07-02 19:48:45 +00:00
TargetOpcodes.h
TargetOptions.h	Add support for the --param ssp-buffer-size= driver option.	2012-08-21 16:15:24 +00:00
TargetRegisterInfo.h	Add TargetRegisterInfo::hasRegUnit().	2012-08-02 14:45:53 +00:00
TargetSchedule.td	Added MispredictPenalty to SchedMachineModel.	2012-08-08 02:44:16 +00:00
TargetSelectionDAG.td	Remove extra MayLoad/MayStore flags from atomic_load/store.	2012-08-28 03:11:32 +00:00
TargetSelectionDAGInfo.h
TargetSubtargetInfo.h