mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c4d3f662fc
busted in both encoders. I'm not bothering to fix it in the old one at this point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95947 91177308-0d34-0410-b5e6-96231b3b80d8
583 lines
20 KiB
C++
583 lines
20 KiB
C++
//===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86MCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "x86-emitter"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// FIXME: This should move to a header.
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namespace llvm {
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namespace X86 {
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enum Fixups {
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reloc_pcrel_4byte = FirstTargetFixupKind, // 32-bit pcrel, e.g. a branch.
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reloc_pcrel_1byte // 8-bit pcrel, e.g. branch_1
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};
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}
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}
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namespace {
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class X86MCCodeEmitter : public MCCodeEmitter {
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X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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bool Is64BitMode;
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public:
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X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
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: TM(tm), TII(*TM.getInstrInfo()) {
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Is64BitMode = is64Bit;
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}
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~X86MCCodeEmitter() {}
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unsigned getNumFixupKinds() const {
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return 2;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[] = {
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{ "reloc_pcrel_4byte", 0, 4 * 8 },
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{ "reloc_pcrel_1byte", 0, 1 * 8 }
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};
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if (Kind < FirstTargetFixupKind)
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return MCCodeEmitter::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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static unsigned GetX86RegNum(const MCOperand &MO) {
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return X86RegisterInfo::getX86RegNum(MO.getReg());
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}
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void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
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OS << (char)C;
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++CurByte;
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}
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void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
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raw_ostream &OS) const {
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// Output the constant in little endian byte order.
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for (unsigned i = 0; i != Size; ++i) {
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EmitByte(Val & 255, CurByte, OS);
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Val >>= 8;
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}
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}
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void EmitImmediate(const MCOperand &Disp, unsigned ImmSize,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
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unsigned &CurByte, raw_ostream &OS) const {
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EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
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}
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void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
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unsigned &CurByte, raw_ostream &OS) const {
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// SIB byte is in the same format as the ModRMByte.
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EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
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}
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void EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
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TargetMachine &TM) {
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return new X86MCCodeEmitter(TM, false);
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}
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MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
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TargetMachine &TM) {
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return new X86MCCodeEmitter(TM, true);
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}
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/// isDisp8 - Return true if this signed displacement fits in a 8-bit
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/// sign-extended field.
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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void X86MCCodeEmitter::
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EmitImmediate(const MCOperand &DispOp, unsigned Size,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// If this is a simple integer displacement that doesn't require a relocation,
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// emit it now.
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if (DispOp.isImm()) {
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EmitConstant(DispOp.getImm(), Size, CurByte, OS);
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return;
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}
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// FIXME: Pass in the relocation type, this is just a hack..
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unsigned FixupKind;
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if (Size == 1)
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FixupKind = FK_Data_1;
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else if (Size == 2)
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FixupKind = FK_Data_2;
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else if (Size == 4)
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FixupKind = FK_Data_4;
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else {
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assert(Size == 8 && "Unknown immediate size");
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FixupKind = FK_Data_8;
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}
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// Emit a symbolic constant as a fixup and 4 zeros.
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Fixups.push_back(MCFixup::Create(CurByte, DispOp.getExpr(),
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MCFixupKind(FixupKind)));
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EmitConstant(0, Size, CurByte, OS);
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}
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void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField,
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unsigned &CurByte,
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raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const{
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const MCOperand &Disp = MI.getOperand(Op+3);
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const MCOperand &Base = MI.getOperand(Op);
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const MCOperand &Scale = MI.getOperand(Op+1);
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const MCOperand &IndexReg = MI.getOperand(Op+2);
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unsigned BaseReg = Base.getReg();
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unsigned BaseRegNo = -1U;
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if (BaseReg != 0 && BaseReg != X86::RIP)
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BaseRegNo = GetX86RegNum(Base);
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// Determine whether a SIB byte is needed.
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// If no BaseReg, issue a RIP relative instruction only if the MCE can
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// resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
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// 2-7) and absolute references.
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if (// The SIB byte must be used if there is an index register.
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IndexReg.getReg() == 0 &&
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// The SIB byte must be used if the base is ESP/RSP/R12, all of which
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// encode to an R/M value of 4, which indicates that a SIB byte is
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// present.
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BaseRegNo != N86::ESP &&
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// If there is no base register and we're in 64-bit mode, we need a SIB
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// byte to emit an addr that is just 'disp32' (the non-RIP relative form).
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(!Is64BitMode || BaseReg != 0)) {
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if (BaseReg == 0 || // [disp32] in X86-32 mode
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BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
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EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
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EmitImmediate(Disp, 4, CurByte, OS, Fixups);
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return;
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}
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// If the base is not EBP/ESP and there is no displacement, use simple
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// indirect register encoding, this handles addresses like [EAX]. The
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// encoding for [EBP] with no displacement means [disp32] so we handle it
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// by emitting a displacement of 0 below.
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if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
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EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
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return;
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}
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// Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
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if (Disp.isImm() && isDisp8(Disp.getImm())) {
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EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
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EmitImmediate(Disp, 1, CurByte, OS, Fixups);
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return;
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}
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// Otherwise, emit the most general non-SIB encoding: [REG+disp32]
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EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
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EmitImmediate(Disp, 4, CurByte, OS, Fixups);
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return;
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}
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// We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP &&
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IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
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ForceDisp32 = true;
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} else if (!Disp.isImm()) {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
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ForceDisp32 = true;
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} else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
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// Emit no displacement ModR/M byte
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EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
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} else if (isDisp8(Disp.getImm())) {
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// Emit the disp8 encoding.
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EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImm()];
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if (BaseReg == 0) {
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// Handle the SIB byte for the case where there is no base, see Intel
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// Manual 2A, table 2-7. The displacement has already been output.
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = GetX86RegNum(IndexReg);
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else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
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IndexRegNo = 4;
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EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
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} else {
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = GetX86RegNum(IndexReg);
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else
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IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
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EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
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}
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// Do we need to output a displacement?
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if (ForceDisp8)
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EmitImmediate(Disp, 1, CurByte, OS, Fixups);
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else if (ForceDisp32 || Disp.getImm() != 0)
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EmitImmediate(Disp, 4, CurByte, OS, Fixups);
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}
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/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
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/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
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/// size, and 3) use of X86-64 extended registers.
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static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
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const TargetInstrDesc &Desc) {
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// Pseudo instructions shouldn't get here.
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assert((TSFlags & X86II::FormMask) != X86II::Pseudo &&
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"Can't encode pseudo instrs");
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unsigned REX = 0;
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if (TSFlags & X86II::REX_W)
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REX |= 1 << 3;
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if (MI.getNumOperands() == 0) return REX;
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unsigned NumOps = MI.getNumOperands();
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// FIXME: MCInst should explicitize the two-addrness.
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bool isTwoAddr = NumOps > 1 &&
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Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
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// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
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unsigned i = isTwoAddr ? 1 : 0;
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for (; i != NumOps; ++i) {
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const MCOperand &MO = MI.getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
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// FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
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// that returns non-zero.
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REX |= 0x40;
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break;
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}
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switch (TSFlags & X86II::FormMask) {
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case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
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case X86II::MRMSrcReg:
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if (MI.getOperand(0).isReg() &&
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X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
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REX |= 1 << 2;
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i = isTwoAddr ? 2 : 1;
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for (; i != NumOps; ++i) {
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const MCOperand &MO = MI.getOperand(i);
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if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
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REX |= 1 << 0;
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}
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break;
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case X86II::MRMSrcMem: {
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if (MI.getOperand(0).isReg() &&
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X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
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REX |= 1 << 2;
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unsigned Bit = 0;
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i = isTwoAddr ? 2 : 1;
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for (; i != NumOps; ++i) {
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const MCOperand &MO = MI.getOperand(i);
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if (MO.isReg()) {
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if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
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REX |= 1 << Bit;
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Bit++;
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}
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}
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break;
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}
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case X86II::MRM0m: case X86II::MRM1m:
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case X86II::MRM2m: case X86II::MRM3m:
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case X86II::MRM4m: case X86II::MRM5m:
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case X86II::MRM6m: case X86II::MRM7m:
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case X86II::MRMDestMem: {
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unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
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i = isTwoAddr ? 1 : 0;
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if (NumOps > e && MI.getOperand(e).isReg() &&
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X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
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REX |= 1 << 2;
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unsigned Bit = 0;
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for (; i != e; ++i) {
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const MCOperand &MO = MI.getOperand(i);
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if (MO.isReg()) {
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if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
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REX |= 1 << Bit;
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Bit++;
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}
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}
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break;
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}
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default:
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if (MI.getOperand(0).isReg() &&
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X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
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REX |= 1 << 0;
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i = isTwoAddr ? 2 : 1;
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for (unsigned e = NumOps; i != e; ++i) {
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const MCOperand &MO = MI.getOperand(i);
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if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
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REX |= 1 << 2;
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}
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break;
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}
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return REX;
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}
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void X86MCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = TII.get(Opcode);
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unsigned TSFlags = Desc.TSFlags;
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// Keep track of the current byte being emitted.
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unsigned CurByte = 0;
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// FIXME: We should emit the prefixes in exactly the same order as GAS does,
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// in order to provide diffability.
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// Emit the lock opcode prefix as needed.
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if (TSFlags & X86II::LOCK)
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EmitByte(0xF0, CurByte, OS);
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// Emit segment override opcode prefix as needed.
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switch (TSFlags & X86II::SegOvrMask) {
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default: assert(0 && "Invalid segment!");
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case 0: break; // No segment override!
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case X86II::FS:
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EmitByte(0x64, CurByte, OS);
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break;
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case X86II::GS:
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EmitByte(0x65, CurByte, OS);
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break;
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}
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// Emit the repeat opcode prefix as needed.
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if ((TSFlags & X86II::Op0Mask) == X86II::REP)
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EmitByte(0xF3, CurByte, OS);
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// Emit the operand size opcode prefix as needed.
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if (TSFlags & X86II::OpSize)
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EmitByte(0x66, CurByte, OS);
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// Emit the address size opcode prefix as needed.
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if (TSFlags & X86II::AdSize)
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EmitByte(0x67, CurByte, OS);
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bool Need0FPrefix = false;
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switch (TSFlags & X86II::Op0Mask) {
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default: assert(0 && "Invalid prefix!");
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case 0: break; // No prefix!
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case X86II::REP: break; // already handled.
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case X86II::TB: // Two-byte opcode prefix
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case X86II::T8: // 0F 38
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case X86II::TA: // 0F 3A
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Need0FPrefix = true;
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break;
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case X86II::TF: // F2 0F 38
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EmitByte(0xF2, CurByte, OS);
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Need0FPrefix = true;
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break;
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case X86II::XS: // F3 0F
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EmitByte(0xF3, CurByte, OS);
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Need0FPrefix = true;
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break;
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case X86II::XD: // F2 0F
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EmitByte(0xF2, CurByte, OS);
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Need0FPrefix = true;
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break;
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case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
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case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
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case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
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case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
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case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
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case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
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case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
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case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
|
|
}
|
|
|
|
// Handle REX prefix.
|
|
// FIXME: Can this come before F2 etc to simplify emission?
|
|
if (Is64BitMode) {
|
|
if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
|
|
EmitByte(0x40 | REX, CurByte, OS);
|
|
}
|
|
|
|
// 0x0F escape code must be emitted just before the opcode.
|
|
if (Need0FPrefix)
|
|
EmitByte(0x0F, CurByte, OS);
|
|
|
|
// FIXME: Pull this up into previous switch if REX can be moved earlier.
|
|
switch (TSFlags & X86II::Op0Mask) {
|
|
case X86II::TF: // F2 0F 38
|
|
case X86II::T8: // 0F 38
|
|
EmitByte(0x38, CurByte, OS);
|
|
break;
|
|
case X86II::TA: // 0F 3A
|
|
EmitByte(0x3A, CurByte, OS);
|
|
break;
|
|
}
|
|
|
|
// If this is a two-address instruction, skip one of the register operands.
|
|
unsigned NumOps = Desc.getNumOperands();
|
|
unsigned CurOp = 0;
|
|
if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
|
|
++CurOp;
|
|
else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
|
|
// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
|
|
--NumOps;
|
|
|
|
unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
|
|
switch (TSFlags & X86II::FormMask) {
|
|
case X86II::MRMInitReg:
|
|
assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
|
|
default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
|
|
assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
|
|
case X86II::RawFrm:
|
|
EmitByte(BaseOpcode, CurByte, OS);
|
|
break;
|
|
|
|
case X86II::AddRegFrm:
|
|
EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
|
|
break;
|
|
|
|
case X86II::MRMDestReg:
|
|
EmitByte(BaseOpcode, CurByte, OS);
|
|
EmitRegModRMByte(MI.getOperand(CurOp),
|
|
GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
|
|
CurOp += 2;
|
|
break;
|
|
|
|
case X86II::MRMDestMem:
|
|
EmitByte(BaseOpcode, CurByte, OS);
|
|
EmitMemModRMByte(MI, CurOp,
|
|
GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
|
|
CurByte, OS, Fixups);
|
|
CurOp += X86AddrNumOperands + 1;
|
|
break;
|
|
|
|
case X86II::MRMSrcReg:
|
|
EmitByte(BaseOpcode, CurByte, OS);
|
|
EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
|
|
CurByte, OS);
|
|
CurOp += 2;
|
|
break;
|
|
|
|
case X86II::MRMSrcMem: {
|
|
EmitByte(BaseOpcode, CurByte, OS);
|
|
|
|
// FIXME: Maybe lea should have its own form? This is a horrible hack.
|
|
int AddrOperands;
|
|
if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
|
|
Opcode == X86::LEA16r || Opcode == X86::LEA32r)
|
|
AddrOperands = X86AddrNumOperands - 1; // No segment register
|
|
else
|
|
AddrOperands = X86AddrNumOperands;
|
|
|
|
EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
|
|
CurByte, OS, Fixups);
|
|
CurOp += AddrOperands + 1;
|
|
break;
|
|
}
|
|
|
|
case X86II::MRM0r: case X86II::MRM1r:
|
|
case X86II::MRM2r: case X86II::MRM3r:
|
|
case X86II::MRM4r: case X86II::MRM5r:
|
|
case X86II::MRM6r: case X86II::MRM7r:
|
|
EmitByte(BaseOpcode, CurByte, OS);
|
|
|
|
// Special handling of lfence, mfence, monitor, and mwait.
|
|
// FIXME: This is terrible, they should get proper encoding bits in TSFlags.
|
|
if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
|
|
Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
|
|
EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r,
|
|
Opcode == X86::MWAIT),
|
|
CurByte, OS);
|
|
} else {
|
|
EmitRegModRMByte(MI.getOperand(CurOp++),
|
|
(TSFlags & X86II::FormMask)-X86II::MRM0r,
|
|
CurByte, OS);
|
|
}
|
|
break;
|
|
case X86II::MRM0m: case X86II::MRM1m:
|
|
case X86II::MRM2m: case X86II::MRM3m:
|
|
case X86II::MRM4m: case X86II::MRM5m:
|
|
case X86II::MRM6m: case X86II::MRM7m:
|
|
EmitByte(BaseOpcode, CurByte, OS);
|
|
EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
|
|
CurByte, OS, Fixups);
|
|
CurOp += X86AddrNumOperands;
|
|
break;
|
|
}
|
|
|
|
// If there is a remaining operand, it must be a trailing immediate. Emit it
|
|
// according to the right size for the instruction.
|
|
// FIXME: This should pass in whether the value is pc relative or not. This
|
|
// information should be aquired from TSFlags as well.
|
|
if (CurOp != NumOps)
|
|
EmitImmediate(MI.getOperand(CurOp++), X86II::getSizeOfImm(TSFlags),
|
|
CurByte, OS, Fixups);
|
|
|
|
#ifndef NDEBUG
|
|
// FIXME: Verify.
|
|
if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
|
|
errs() << "Cannot encode all operands of: ";
|
|
MI.dump();
|
|
errs() << '\n';
|
|
abort();
|
|
}
|
|
#endif
|
|
}
|