mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b52bf6a3b3
All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.6 KiB
LLVM
71 lines
2.6 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; EG-CHECK-LABEL: @u32_mad24
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; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X
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; SI-CHECK-LABEL: @u32_mad24
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; SI-CHECK: V_MAD_U32_U24
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define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = shl i32 %a, 8
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%a_24 = lshr i32 %0, 8
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%1 = shl i32 %b, 8
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%b_24 = lshr i32 %1, 8
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%2 = mul i32 %a_24, %b_24
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%3 = add i32 %2, %c
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @i16_mad24
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; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
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; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
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; EG-CHECK-DAG: VTX_READ_16 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48
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; The order of A and B does not matter.
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; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]]
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; The result must be sign-extended
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; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x
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; EG-CHECK: 16
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; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
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; EG-CHECK: 16
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; SI-CHECK-LABEL: @i16_mad24
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; SI-CHECK: V_MAD_U32_U24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 16, [[MAD]]
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; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 16, [[LSHL]]
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define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
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entry:
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%0 = mul i16 %a, %b
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%1 = add i16 %0, %c
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%2 = sext i16 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @i8_mad24
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; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
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; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
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; EG-CHECK-DAG: VTX_READ_8 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48
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; The order of A and B does not matter.
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; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]]
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; The result must be sign-extended
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; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x
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; EG-CHECK: 24
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; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
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; EG-CHECK: 24
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; SI-CHECK-LABEL: @i8_mad24
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; SI-CHECK: V_MAD_U32_U24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 24, [[MUL]]
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; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 24, [[LSHL]]
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define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
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entry:
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%0 = mul i8 %a, %b
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%1 = add i8 %0, %c
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%2 = sext i8 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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