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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117180 91177308-0d34-0410-b5e6-96231b3b80d8
182 lines
6.5 KiB
C++
182 lines
6.5 KiB
C++
//===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RegAllocBase class, which is the skeleton of a basic
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// register allocation algorithm and interface for extending it. It provides the
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// building blocks on which to construct other experimental allocators and test
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// the validity of two principles:
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//
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// - If virtual and physical register liveness is modeled using intervals, then
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// on-the-fly interference checking is cheap. Furthermore, interferences can be
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// lazily cached and reused.
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//
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// - Register allocation complexity, and generated code performance is
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// determined by the effectiveness of live range splitting rather than optimal
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// coloring.
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//
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// Following the first principle, interfering checking revolves around the
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// LiveIntervalUnion data structure.
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//
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// To fulfill the second principle, the basic allocator provides a driver for
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// incremental splitting. It essentially punts on the problem of register
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// coloring, instead driving the assignment of virtual to physical registers by
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// the cost of splitting. The basic allocator allows for heuristic reassignment
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// of registers, if a more sophisticated allocator chooses to do that.
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//
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// This framework provides a way to engineer the compile time vs. code
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// quality trade-off without relying a particular theoretical solver.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_REGALLOCBASE
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#define LLVM_CODEGEN_REGALLOCBASE
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#include "LiveIntervalUnion.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/OwningPtr.h"
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#include <vector>
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#include <queue>
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namespace llvm {
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class VirtRegMap;
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/// RegAllocBase provides the register allocation driver and interface that can
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/// be extended to add interesting heuristics.
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///
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/// More sophisticated allocators must override the selectOrSplit() method to
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/// implement live range splitting and must specify a comparator to determine
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/// register assignment priority. LessSpillWeightPriority is provided as a
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/// standard comparator.
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class RegAllocBase {
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protected:
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typedef SmallVector<LiveInterval*, 4> LiveVirtRegs;
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typedef LiveVirtRegs::iterator LVRIter;
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// Array of LiveIntervalUnions indexed by physical register.
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class LIUArray {
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unsigned nRegs_;
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OwningArrayPtr<LiveIntervalUnion> array_;
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public:
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LIUArray(): nRegs_(0) {}
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unsigned numRegs() const { return nRegs_; }
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void init(unsigned nRegs);
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void clear();
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LiveIntervalUnion& operator[](unsigned physReg) {
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assert(physReg < nRegs_ && "physReg out of bounds");
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return array_[physReg];
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}
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};
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const TargetRegisterInfo *tri_;
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VirtRegMap *vrm_;
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LiveIntervals *lis_;
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LIUArray physReg2liu_;
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RegAllocBase(): tri_(0), vrm_(0), lis_(0) {}
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virtual ~RegAllocBase() {}
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// A RegAlloc pass should call this before allocatePhysRegs.
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void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
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// The top-level driver. Specialize with the comparator that determines the
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// priority of assigning live virtual registers. The output is a VirtRegMap
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// that us updated with physical register assignments.
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template<typename LICompare>
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void allocatePhysRegs(LICompare liCompare);
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// A RegAlloc pass should override this to provide the allocation heuristics.
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// Each call must guarantee forward progess by returning an available
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// PhysReg or new set of split LiveVirtRegs. It is up to the splitter to
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// converge quickly toward fully spilled live ranges.
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virtual unsigned selectOrSplit(LiveInterval &lvr,
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LiveVirtRegs &splitLVRs) = 0;
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// A RegAlloc pass should call this when PassManager releases its memory.
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virtual void releaseMemory();
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// Helper for checking interference between a live virtual register and a
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// physical register, including all its register aliases.
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bool checkPhysRegInterference(LiveIntervalUnion::Query &query, unsigned preg);
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private:
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template<typename PQ>
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void seedLiveVirtRegs(PQ &lvrQ);
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};
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// Heuristic that determines the priority of assigning virtual to physical
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// registers. The main impact of the heuristic is expected to be compile time.
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// The default is to simply compare spill weights.
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struct LessSpillWeightPriority
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: public std::binary_function<LiveInterval,LiveInterval, bool> {
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bool operator()(const LiveInterval *left, const LiveInterval *right) const {
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return left->weight < right->weight;
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}
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};
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// Visit all the live virtual registers. If they are already assigned to a
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// physical register, unify them with the corresponding LiveIntervalUnion,
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// otherwise push them on the priority queue for later assignment.
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template<typename PQ>
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void RegAllocBase::seedLiveVirtRegs(PQ &lvrQ) {
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for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end();
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liItr != liEnd; ++liItr) {
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unsigned reg = liItr->first;
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LiveInterval &li = *liItr->second;
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if (TargetRegisterInfo::isPhysicalRegister(reg)) {
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physReg2liu_[reg].unify(li);
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}
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else {
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lvrQ.push(&li);
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}
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}
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}
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// Top-level driver to manage the queue of unassigned LiveVirtRegs and call the
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// selectOrSplit implementation.
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template<typename LICompare>
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void RegAllocBase::allocatePhysRegs(LICompare liCompare) {
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typedef std::priority_queue
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<LiveInterval*, std::vector<LiveInterval*>, LICompare> LiveVirtRegQueue;
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LiveVirtRegQueue lvrQ(liCompare);
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seedLiveVirtRegs(lvrQ);
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while (!lvrQ.empty()) {
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LiveInterval *lvr = lvrQ.top();
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lvrQ.pop();
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LiveVirtRegs splitLVRs;
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unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs);
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if (availablePhysReg) {
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assert(splitLVRs.empty() && "inconsistent splitting");
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assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions");
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vrm_->assignVirt2Phys(lvr->reg, availablePhysReg);
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physReg2liu_[availablePhysReg].unify(*lvr);
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}
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else {
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for (LVRIter lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end();
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lvrI != lvrEnd; ++lvrI ) {
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assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) &&
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"expect split value in virtual register");
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lvrQ.push(*lvrI);
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}
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}
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}
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}
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} // end namespace llvm
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#endif // !defined(LLVM_CODEGEN_REGALLOCBASE)
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