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https://github.com/c64scene-ar/llvm-6502.git
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82fe467ca5
such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110035 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.0 KiB
LLVM
58 lines
1.0 KiB
LLVM
;RUN: llc --march=cellspu %s -o - | FileCheck %s
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%vec = type <2 x i32>
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define %vec @test_ret(%vec %param)
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{
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;CHECK: bi $lr
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ret %vec %param
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}
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define %vec @test_add(%vec %param)
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{
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;CHECK: a $3, $3, $3
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%1 = add %vec %param, %param
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;CHECK: bi $lr
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ret %vec %1
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}
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define %vec @test_sub(%vec %param)
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{
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;CHECK: sf $3, $4, $3
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%1 = sub %vec %param, <i32 1, i32 1>
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;CHECK: bi $lr
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ret %vec %1
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}
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define %vec @test_mul(%vec %param)
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{
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;CHECK: mpyu
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;CHECK: mpyh
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;CHECK: a
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;CHECK: a $3
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%1 = mul %vec %param, %param
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;CHECK: bi $lr
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ret %vec %1
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}
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define <2 x i32> @test_splat(i32 %param ) {
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;TODO insertelement transforms to a PREFSLOT2VEC, that trasforms to the
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; somewhat redundant:
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;CHECK-NOT or $3, $3, $3
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;CHECK: lqa
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;CHECK: shufb
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%sv = insertelement <1 x i32> undef, i32 %param, i32 0
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%rv = shufflevector <1 x i32> %sv, <1 x i32> undef, <2 x i32> zeroinitializer
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;CHECK: bi $lr
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ret <2 x i32> %rv
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}
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define i32 @test_extract() {
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;CHECK: shufb $3
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%rv = extractelement <2 x i32> zeroinitializer, i32 undef ; <i32> [#uses=1]
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;CHECK: bi $lr
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ret i32 %rv
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}
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