llvm-6502/test/CodeGen
Chandler Carruth c57e90422f [x86] Teach the unpack lowering how to lower with an initial unpack in
addition to lowering to trees rooted in an unpack.

This saves shuffles and or registers in many various ways, lets us
handle another class of v4i32 shuffles pre SSE4.1 without domain
crosses, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229856 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-19 15:06:13 +00:00
..
AArch64 AArch64: Safely handle the incoming sret call argument. 2015-02-16 18:10:47 +00:00
ARM llvm-mc: Use Target::createNullStreamer to fix crashes on target-specific asm directives. 2015-02-19 00:45:04 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips [mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator 2015-02-19 11:51:32 +00:00
MSP430
NVPTX
PowerPC This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions. 2015-02-18 16:21:46 +00:00
R600 R600/SI: Add missing offset operand to buffer bothen 2015-02-18 02:04:38 +00:00
SPARC SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too 2015-02-16 21:47:58 +00:00
SystemZ [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
Thumb
Thumb2
X86 [x86] Teach the unpack lowering how to lower with an initial unpack in 2015-02-19 15:06:13 +00:00
XCore