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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
2.8 KiB
LLVM
82 lines
2.8 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
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; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).
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; This is already checked for in Atomics-64.ll
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; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc64 | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
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; In this file, we check that atomic load/store can make use of the indexed
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; versions of the instructions.
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; Indexed version of loads
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define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
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; CHECK-LABEL: load_x_i8_seq_cst
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; CHECK: sync 0
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; CHECK: lbzx
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; CHECK: sync 1
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%ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
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%val = load atomic i8, i8* %ptr seq_cst, align 1
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ret i8 %val
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}
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define i16 @load_x_i16_acquire([100000 x i16]* %mem) {
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; CHECK-LABEL: load_x_i16_acquire
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; CHECK: lhzx
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; CHECK: sync 1
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%ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
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%val = load atomic i16, i16* %ptr acquire, align 2
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ret i16 %val
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}
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define i32 @load_x_i32_monotonic([100000 x i32]* %mem) {
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; CHECK-LABEL: load_x_i32_monotonic
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; CHECK: lwzx
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; CHECK-NOT: sync
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%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
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%val = load atomic i32, i32* %ptr monotonic, align 4
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ret i32 %val
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}
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define i64 @load_x_i64_unordered([100000 x i64]* %mem) {
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; CHECK-LABEL: load_x_i64_unordered
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: ldx
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; CHECK-NOT: sync
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%ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
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%val = load atomic i64, i64* %ptr unordered, align 8
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ret i64 %val
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}
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; Indexed version of stores
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define void @store_x_i8_seq_cst([100000 x i8]* %mem) {
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; CHECK-LABEL: store_x_i8_seq_cst
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; CHECK: sync 0
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; CHECK: stbx
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%ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
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store atomic i8 42, i8* %ptr seq_cst, align 1
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ret void
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}
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define void @store_x_i16_release([100000 x i16]* %mem) {
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; CHECK-LABEL: store_x_i16_release
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; CHECK: sync 1
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; CHECK: sthx
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%ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
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store atomic i16 42, i16* %ptr release, align 2
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ret void
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}
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define void @store_x_i32_monotonic([100000 x i32]* %mem) {
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; CHECK-LABEL: store_x_i32_monotonic
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; CHECK-NOT: sync
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; CHECK: stwx
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%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
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store atomic i32 42, i32* %ptr monotonic, align 4
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ret void
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}
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define void @store_x_i64_unordered([100000 x i64]* %mem) {
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; CHECK-LABEL: store_x_i64_unordered
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; CHECK-NOT: sync 0
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; CHECK-NOT: sync 1
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: stdx
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%ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
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store atomic i64 42, i64* %ptr unordered, align 8
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ret void
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}
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