Jim Grosbach c5a8c861c9 ARM extend instructions simplification. ...

Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8

2011-07-27 16:47:19 +00:00

..

Analysis

Explicitly cast narrowing conversions inside {}s that will become errors in

2011-07-27 06:22:51 +00:00

Archive

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AsmParser

Initial implementation of 'fence' instruction, the new C++0x-style replacement for llvm.memory.barrier.

2011-07-25 23:16:38 +00:00

Bitcode

Initial implementation of 'fence' instruction, the new C++0x-style replacement for llvm.memory.barrier.

2011-07-25 23:16:38 +00:00

CodeGen

Explicitly cast narrowing conversions inside {}s that will become errors in

2011-07-27 06:22:51 +00:00

CompilerDriver

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ExecutionEngine

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Linker

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MC

Support .code32 and .code64 in X86 assembler.

2011-07-27 00:38:12 +00:00

Object

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Support

Optimize 96-bit division a little bit.

2011-07-27 16:00:40 +00:00

Target

ARM extend instructions simplification.

2011-07-27 16:47:19 +00:00

Transforms

Misc mid-level changes for new 'fence' instruction.

2011-07-27 01:08:30 +00:00

VMCore

Misc mid-level changes for new 'fence' instruction.

2011-07-27 01:08:30 +00:00

CMakeLists.txt

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Makefile

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