Evan Cheng 66a48bbc35 Teach tblgen to accept register source operands in patterns, e.g. ... def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), "shl{b} {%cl, $dst|$dst, %CL}", [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>; This generates a CopyToReg operand and added its 2nd result to the shl as a flag operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24557 91177308-0d34-0410-b5e6-96231b3b80d8		2005-12-01 00:18:45 +00:00
..
AsmPrinter.h	Add a new flag	2005-11-21 23:06:08 +00:00
ELFWriter.h
InstrScheduling.h
IntrinsicLowering.h	add a flag	2005-11-16 07:21:15 +00:00
LiveInterval.h	add a new method	2005-10-20 07:37:59 +00:00
LiveIntervalAnalysis.h	add missing prototype	2005-10-21 15:49:28 +00:00
LiveVariables.h	Fix a problem Duraid noticed, where we weren't removing values from the kills	2005-08-25 05:45:31 +00:00
MachineBasicBlock.h
MachineCodeEmitter.h
MachineConstantPool.h
MachineFrameInfo.h	Change a comment slightly	2005-11-06 17:40:18 +00:00
MachineFunction.h	remove an inappropriate comment	2005-08-31 22:49:51 +00:00
MachineFunctionPass.h
MachineInstr.h
MachineInstrBuilder.h
MachineRelocation.h
Passes.h	Remove a prototype	2005-10-24 04:13:21 +00:00
SchedGraphCommon.h
SelectionDAG.h	Teach tblgen to accept register source operands in patterns, e.g.	2005-12-01 00:18:45 +00:00
SelectionDAGISel.h
SelectionDAGNodes.h	Added an index field to GlobalAddressSDNode so it can represent X+12, etc.	2005-11-30 02:04:11 +00:00
SSARegMap.h
ValueSet.h
ValueTypes.h	First chunk of actually generating vector code for packed types. These	2005-11-30 08:22:07 +00:00