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RA problem by expanding the live interval of an earlyclobber def back one slot. Remove overlap-earlyclobber throughout. Remove earlyclobber bits and their handling from live internals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56539 91177308-0d34-0410-b5e6-96231b3b80d8
697 lines
27 KiB
C++
697 lines
27 KiB
C++
//===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the Emit routines for the ScheduleDAG class, which creates
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// MachineInstrs according to the computed schedule.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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STATISTIC(NumCommutes, "Number of instructions commuted");
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/// getInstrOperandRegClass - Return register class of the operand of an
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/// instruction of the specified TargetInstrDesc.
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static const TargetRegisterClass*
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getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII, const TargetInstrDesc &II,
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unsigned Op) {
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if (Op >= II.getNumOperands()) {
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assert(II.isVariadic() && "Invalid operand # of instruction");
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return NULL;
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}
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if (II.OpInfo[Op].isLookupPtrRegClass())
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return TII->getPointerRegClass();
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return TRI->getRegClass(II.OpInfo[Op].RegClass);
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}
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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bool IsClone, unsigned SrcReg,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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unsigned VRBase = 0;
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if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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// Just use the input register directly!
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SDValue Op(Node, ResNo);
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if (IsClone)
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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return;
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}
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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bool MatchReg = true;
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const TargetRegisterClass *UseRC = NULL;
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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bool Match = true;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == ResNo) {
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unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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Match = false;
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} else if (DestReg != SrcReg)
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Match = false;
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} else {
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for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
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SDValue Op = User->getOperand(i);
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if (Op.getNode() != Node || Op.getResNo() != ResNo)
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continue;
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MVT VT = Node->getValueType(Op.getResNo());
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if (VT == MVT::Other || VT == MVT::Flag)
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continue;
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Match = false;
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if (User->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
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if (!UseRC)
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UseRC = RC;
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else if (RC)
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assert(UseRC == RC &&
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"Multiple uses expecting different register classes!");
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}
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}
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}
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MatchReg &= Match;
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if (VRBase)
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break;
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}
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MVT VT = Node->getValueType(ResNo);
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const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
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SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
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// Figure out the register class to create for the destreg.
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if (VRBase) {
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DstRC = MRI.getRegClass(VRBase);
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} else if (UseRC) {
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assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
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DstRC = UseRC;
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} else {
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DstRC = TLI->getRegClassFor(VT);
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}
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// If all uses are reading from the src physical register and copying the
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// register is either impossible or very expensive, then don't create a copy.
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if (MatchReg && SrcRC->getCopyCost() < 0) {
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VRBase = SrcReg;
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} else {
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// Create the reg, emit the copy.
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VRBase = MRI.createVirtualRegister(DstRC);
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bool Emitted =
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TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
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Emitted = Emitted; // Silence compiler warning.
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assert(Emitted && "Unable to issue a copy instruction!");
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}
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SDValue Op(Node, ResNo);
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if (IsClone)
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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}
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/// getDstOfCopyToRegUse - If the only use of the specified result number of
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/// node is a CopyToReg, return its destination register. Return 0 otherwise.
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unsigned ScheduleDAG::getDstOfOnlyCopyToRegUse(SDNode *Node,
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unsigned ResNo) const {
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if (!Node->hasOneUse())
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return 0;
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SDNode *User = *Node->use_begin();
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == ResNo) {
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return Reg;
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}
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return 0;
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}
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void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
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"IMPLICIT_DEF should have been handled as a special case elsewhere!");
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for (unsigned i = 0; i < II.getNumDefs(); ++i) {
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// If the specific node value is only used by a CopyToReg and the dest reg
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// is a vreg, use the CopyToReg'd destination register instead of creating
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// a new vreg.
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unsigned VRBase = 0;
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == i) {
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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VRBase = Reg;
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MI->addOperand(MachineOperand::CreateReg(Reg, true));
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break;
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}
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}
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}
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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if (VRBase == 0) {
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const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
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assert(RC && "Isn't a register operand!");
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VRBase = MRI.createVirtualRegister(RC);
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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SDValue Op(Node, i);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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}
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}
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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unsigned ScheduleDAG::getVR(SDValue Op,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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if (Op.isMachineOpcode() &&
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Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
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// Add an IMPLICIT_DEF instruction before every use.
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unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
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// IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
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// does not include operand register class info.
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if (!VReg) {
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const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
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VReg = MRI.createVirtualRegister(RC);
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}
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BuildMI(BB, TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg);
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return VReg;
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}
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DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
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assert(I != VRBaseMap.end() && "Node emitted out of order - late");
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return I->second;
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}
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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if (Op.isMachineOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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// simpler here.
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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// Get/emit the operand.
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unsigned VReg = getVR(Op, VRBaseMap);
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const TargetInstrDesc &TID = MI->getDesc();
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bool isOptDef = IIOpNum < TID.getNumOperands() &&
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TID.OpInfo[IIOpNum].isOptionalDef();
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MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
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// Verify that it is right.
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assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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#ifndef NDEBUG
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if (II) {
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// There may be no register class for this operand if it is a variadic
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// argument (RC will be NULL in this case). In this case, we just assume
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// the regclass is ok.
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
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assert((RC || II->isVariadic()) && "Expected reg class info!");
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const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
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if (RC && VRC != RC) {
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cerr << "Register class of operand and regclass of use don't agree!\n";
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cerr << "Operand = " << IIOpNum << "\n";
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cerr << "Op->Val = "; Op.getNode()->dump(&DAG); cerr << "\n";
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cerr << "MI = "; MI->print(cerr);
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cerr << "VReg = " << VReg << "\n";
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cerr << "VReg RegClass size = " << VRC->getSize()
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<< ", align = " << VRC->getAlignment() << "\n";
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cerr << "Expected RegClass size = " << RC->getSize()
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<< ", align = " << RC->getAlignment() << "\n";
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cerr << "Fatal error, aborting.\n";
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abort();
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}
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}
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#endif
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} else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
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} else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
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const ConstantFP *CFP = F->getConstantFPValue();
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MI->addOperand(MachineOperand::CreateFPImm(CFP));
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} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
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} else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
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} else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
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} else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
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} else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
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int Offset = CP->getOffset();
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unsigned Align = CP->getAlignment();
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const Type *Type = CP->getType();
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// MachineConstantPool wants an explicit alignment.
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if (Align == 0) {
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Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
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if (Align == 0) {
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// Alignment of vector types. FIXME!
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Align = TM.getTargetData()->getABITypeSize(Type);
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Align = Log2_64(Align);
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}
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}
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unsigned Idx;
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if (CP->isMachineConstantPoolEntry())
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Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
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else
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Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
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MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
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} else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
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} else {
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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unsigned VReg = getVR(Op, VRBaseMap);
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MI->addOperand(MachineOperand::CreateReg(VReg, false));
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// Verify that it is right. Note that the reg class of the physreg and the
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// vreg don't necessarily need to match, but the target copy insertion has
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// to be able to handle it. This handles things like copies from ST(0) to
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// an FP vreg on x86.
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assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II && !II->isVariadic()) {
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assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
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"Don't have operand info for this instruction!");
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}
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}
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}
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void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
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MI->addMemOperand(*MF, MO);
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}
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/// getSubRegisterRegClass - Returns the register class of specified register
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/// class' "SubIdx"'th sub-register class.
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static const TargetRegisterClass*
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getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) {
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// Pick the register class of the subregister
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TargetRegisterInfo::regclass_iterator I =
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TRC->subregclasses_begin() + SubIdx-1;
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assert(I < TRC->subregclasses_end() &&
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"Invalid subregister index for register class");
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return *I;
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}
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/// getSuperRegisterRegClass - Returns the register class of a superreg A whose
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/// "SubIdx"'th sub-register class is the specified register class and whose
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/// type matches the specified type.
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static const TargetRegisterClass*
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getSuperRegisterRegClass(const TargetRegisterClass *TRC,
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unsigned SubIdx, MVT VT) {
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// Pick the register class of the superegister for this type
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for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
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E = TRC->superregclasses_end(); I != E; ++I)
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if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
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return *I;
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assert(false && "Couldn't find the register class");
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return 0;
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}
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/// EmitSubregNode - Generate machine code for subreg nodes.
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///
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void ScheduleDAG::EmitSubregNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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unsigned VRBase = 0;
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unsigned Opc = Node->getMachineOpcode();
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node) {
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unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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break;
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}
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}
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}
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if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
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unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
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// Create the extract_subreg machine instruction.
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MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
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// Figure out the register class to create for the destreg.
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unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
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const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
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const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
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if (VRBase) {
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// Grab the destination register
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#ifndef NDEBUG
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const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
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assert(SRC && DRC && SRC == DRC &&
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"Source subregister and destination must have the same class");
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#endif
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} else {
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// Create the reg
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assert(SRC && "Couldn't find source register class");
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VRBase = MRI.createVirtualRegister(SRC);
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}
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// Add def, source, and subreg index
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
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MI->addOperand(MachineOperand::CreateImm(SubIdx));
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BB->push_back(MI);
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} else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
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Opc == TargetInstrInfo::SUBREG_TO_REG) {
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SDValue N0 = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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SDValue N2 = Node->getOperand(2);
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unsigned SubReg = getVR(N1, VRBaseMap);
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unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
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// Figure out the register class to create for the destreg.
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const TargetRegisterClass *TRC = 0;
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if (VRBase) {
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TRC = MRI.getRegClass(VRBase);
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} else {
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TRC = getSuperRegisterRegClass(MRI.getRegClass(SubReg), SubIdx,
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Node->getValueType(0));
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assert(TRC && "Couldn't determine register class for insert_subreg");
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VRBase = MRI.createVirtualRegister(TRC); // Create the reg
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}
|
|
|
|
// Create the insert_subreg or subreg_to_reg machine instruction.
|
|
MachineInstr *MI = BuildMI(*MF, TII->get(Opc));
|
|
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
|
|
|
|
// If creating a subreg_to_reg, then the first input operand
|
|
// is an implicit value immediate, otherwise it's a register
|
|
if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
|
|
const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
|
|
MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
|
|
} else
|
|
AddOperand(MI, N0, 0, 0, VRBaseMap);
|
|
// Add the subregster being inserted
|
|
AddOperand(MI, N1, 0, 0, VRBaseMap);
|
|
MI->addOperand(MachineOperand::CreateImm(SubIdx));
|
|
BB->push_back(MI);
|
|
} else
|
|
assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
|
|
|
|
SDValue Op(Node, 0);
|
|
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
|
|
isNew = isNew; // Silence compiler warning.
|
|
assert(isNew && "Node emitted out of order - early");
|
|
}
|
|
|
|
/// EmitNode - Generate machine code for an node and needed dependencies.
|
|
///
|
|
void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap) {
|
|
// If machine instruction
|
|
if (Node->isMachineOpcode()) {
|
|
unsigned Opc = Node->getMachineOpcode();
|
|
|
|
// Handle subreg insert/extract specially
|
|
if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
|
|
Opc == TargetInstrInfo::INSERT_SUBREG ||
|
|
Opc == TargetInstrInfo::SUBREG_TO_REG) {
|
|
EmitSubregNode(Node, VRBaseMap);
|
|
return;
|
|
}
|
|
|
|
if (Opc == TargetInstrInfo::IMPLICIT_DEF)
|
|
// We want a unique VR for each IMPLICIT_DEF use.
|
|
return;
|
|
|
|
const TargetInstrDesc &II = TII->get(Opc);
|
|
unsigned NumResults = CountResults(Node);
|
|
unsigned NodeOperands = CountOperands(Node);
|
|
unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
|
|
bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
|
|
II.getImplicitDefs() != 0;
|
|
#ifndef NDEBUG
|
|
unsigned NumMIOperands = NodeOperands + NumResults;
|
|
assert((II.getNumOperands() == NumMIOperands ||
|
|
HasPhysRegOuts || II.isVariadic()) &&
|
|
"#operands for dag node doesn't match .td file!");
|
|
#endif
|
|
|
|
// Create the new machine instruction.
|
|
MachineInstr *MI = BuildMI(*MF, II);
|
|
|
|
// Add result register values for things that are defined by this
|
|
// instruction.
|
|
if (NumResults)
|
|
CreateVirtualRegisters(Node, MI, II, VRBaseMap);
|
|
|
|
// Emit all of the actual operands of this instruction, adding them to the
|
|
// instruction as appropriate.
|
|
for (unsigned i = 0; i != NodeOperands; ++i)
|
|
AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
|
|
|
|
// Emit all of the memory operands of this instruction
|
|
for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
|
|
AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
|
|
|
|
// Commute node if it has been determined to be profitable.
|
|
if (CommuteSet.count(Node)) {
|
|
MachineInstr *NewMI = TII->commuteInstruction(MI);
|
|
if (NewMI == 0)
|
|
DOUT << "Sched: COMMUTING FAILED!\n";
|
|
else {
|
|
DOUT << "Sched: COMMUTED TO: " << *NewMI;
|
|
if (MI != NewMI) {
|
|
MF->DeleteMachineInstr(MI);
|
|
MI = NewMI;
|
|
}
|
|
++NumCommutes;
|
|
}
|
|
}
|
|
|
|
if (II.usesCustomDAGSchedInsertionHook())
|
|
// Insert this instruction into the basic block using a target
|
|
// specific inserter which may returns a new basic block.
|
|
BB = TLI->EmitInstrWithCustomInserter(MI, BB);
|
|
else
|
|
BB->push_back(MI);
|
|
|
|
// Additional results must be an physical register def.
|
|
if (HasPhysRegOuts) {
|
|
for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
|
|
unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
|
|
if (Node->hasAnyUseOfValue(i))
|
|
EmitCopyFromReg(Node, i, IsClone, Reg, VRBaseMap);
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
switch (Node->getOpcode()) {
|
|
default:
|
|
#ifndef NDEBUG
|
|
Node->dump(&DAG);
|
|
#endif
|
|
assert(0 && "This target-independent node should have been selected!");
|
|
break;
|
|
case ISD::EntryToken:
|
|
assert(0 && "EntryToken should have been excluded from the schedule!");
|
|
break;
|
|
case ISD::TokenFactor: // fall thru
|
|
break;
|
|
case ISD::CopyToReg: {
|
|
unsigned SrcReg;
|
|
SDValue SrcVal = Node->getOperand(2);
|
|
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
|
|
SrcReg = R->getReg();
|
|
else
|
|
SrcReg = getVR(SrcVal, VRBaseMap);
|
|
|
|
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
|
|
break;
|
|
|
|
const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
|
|
// Get the register classes of the src/dst.
|
|
if (TargetRegisterInfo::isVirtualRegister(SrcReg))
|
|
SrcTRC = MRI.getRegClass(SrcReg);
|
|
else
|
|
SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(DestReg))
|
|
DstTRC = MRI.getRegClass(DestReg);
|
|
else
|
|
DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
|
|
Node->getOperand(1).getValueType());
|
|
TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
|
|
break;
|
|
}
|
|
case ISD::CopyFromReg: {
|
|
unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
|
|
break;
|
|
}
|
|
case ISD::INLINEASM: {
|
|
unsigned NumOps = Node->getNumOperands();
|
|
if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
|
|
--NumOps; // Ignore the flag operand.
|
|
|
|
// Create the inline asm machine instruction.
|
|
MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::INLINEASM));
|
|
|
|
// Add the asm string as an external symbol operand.
|
|
const char *AsmStr =
|
|
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
|
|
MI->addOperand(MachineOperand::CreateES(AsmStr));
|
|
|
|
// Add all of the operand registers to the instruction.
|
|
for (unsigned i = 2; i != NumOps;) {
|
|
unsigned Flags =
|
|
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
|
|
unsigned NumVals = Flags >> 3;
|
|
|
|
MI->addOperand(MachineOperand::CreateImm(Flags));
|
|
++i; // Skip the ID value.
|
|
|
|
switch (Flags & 7) {
|
|
default: assert(0 && "Bad flags!");
|
|
case 2: // Def of register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
MI->addOperand(MachineOperand::CreateReg(Reg, true));
|
|
}
|
|
break;
|
|
case 6: // Def of earlyclobber register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
|
|
false, 0, true));
|
|
}
|
|
break;
|
|
case 1: // Use of register.
|
|
case 3: // Immediate.
|
|
case 4: // Addressing mode.
|
|
// The addressing mode has been selected, just add all of the
|
|
// operands to the machine instruction.
|
|
for (; NumVals; --NumVals, ++i)
|
|
AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
|
|
break;
|
|
}
|
|
}
|
|
BB->push_back(MI);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void ScheduleDAG::EmitNoop() {
|
|
TII->insertNoop(*BB, BB->end());
|
|
}
|
|
|
|
void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
|
|
DenseMap<SUnit*, unsigned> &VRBaseMap) {
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl) continue; // ignore chain preds
|
|
if (!I->Dep->Node) {
|
|
// Copy to physical register.
|
|
DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->Dep);
|
|
assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
|
|
// Find the destination physical register.
|
|
unsigned Reg = 0;
|
|
for (SUnit::const_succ_iterator II = SU->Succs.begin(),
|
|
EE = SU->Succs.end(); II != EE; ++II) {
|
|
if (I->Reg) {
|
|
Reg = I->Reg;
|
|
break;
|
|
}
|
|
}
|
|
assert(I->Reg && "Unknown physical register!");
|
|
TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
|
|
SU->CopyDstRC, SU->CopySrcRC);
|
|
} else {
|
|
// Copy from physical register.
|
|
assert(I->Reg && "Unknown physical register!");
|
|
unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
|
|
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
|
|
isNew = isNew; // Silence compiler warning.
|
|
assert(isNew && "Node emitted out of order - early");
|
|
TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
|
|
SU->CopyDstRC, SU->CopySrcRC);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
/// EmitSchedule - Emit the machine code in scheduled order.
|
|
MachineBasicBlock *ScheduleDAG::EmitSchedule() {
|
|
DenseMap<SDValue, unsigned> VRBaseMap;
|
|
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
SUnit *SU = Sequence[i];
|
|
if (!SU) {
|
|
// Null SUnit* is a noop.
|
|
EmitNoop();
|
|
continue;
|
|
}
|
|
for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; ++j)
|
|
EmitNode(SU->FlaggedNodes[j], SU->OrigNode != SU, VRBaseMap);
|
|
if (!SU->Node)
|
|
EmitCrossRCCopy(SU, CopyVRBaseMap);
|
|
else
|
|
EmitNode(SU->Node, SU->OrigNode != SU, VRBaseMap);
|
|
}
|
|
|
|
return BB;
|
|
}
|