David Majnemer c5edbea4e7 [InstCombine] (mul nsw 1, INT_MIN) != (shl nsw 1, 31) ... Multiplying INT_MIN by 1 doesn't trigger nsw. However, shifting 1 into the sign bit *does* trigger nsw. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235250 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-18 04:41:30 +00:00
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CodeGen	[GlobalMerge] Look at uses to create smaller global sets.	2015-04-18 01:21:58 +00:00
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IR	DebugInfo: Remove DIDescriptor from the DebugInfo API	2015-04-17 23:20:10 +00:00
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Target	[AArch64] Don't force MVT::Untyped when selecting LD1LANEpost.	2015-04-17 23:43:33 +00:00
Transforms	[InstCombine] (mul nsw 1, INT_MIN) != (shl nsw 1, 31)	2015-04-18 04:41:30 +00:00
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