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https://github.com/c64scene-ar/llvm-6502.git
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d847124211
the same condition, it's important to make sure they are scheduled together to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms IT blocks early (by re-scheduling instructions and split basic blocks) to attempt to fix this. This is not turned on by default since I am not sure this is the right fix. Another issue is llvm selects are modeled as two-address conditional moves. This can be very bad when the copies before the conditional moves are not coalesced away. Teach IT formation pass to move the copies above the IT block (when legal) to avoid breaking the IT block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105669 91177308-0d34-0410-b5e6-96231b3b80d8
126 lines
3.2 KiB
C++
126 lines
3.2 KiB
C++
//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// ARM back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_ARM_H
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#define TARGET_ARM_H
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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namespace llvm {
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class ARMBaseTargetMachine;
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class FunctionPass;
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class JITCodeEmitter;
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class formatted_raw_ostream;
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// Enums corresponding to ARM condition codes
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namespace ARMCC {
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// The CondCodes constants map directly to the 4-bit encoding of the
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// condition field for predicated instructions.
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enum CondCodes {
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EQ,
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NE,
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HS,
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LO,
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MI,
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PL,
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VS,
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VC,
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HI,
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LS,
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GE,
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LT,
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GT,
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LE,
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AL
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};
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inline static CondCodes getOppositeCondition(CondCodes CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return NE;
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case NE: return EQ;
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case HS: return LO;
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case LO: return HS;
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case MI: return PL;
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case PL: return MI;
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case VS: return VC;
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case VC: return VS;
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case HI: return LS;
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case LS: return HI;
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case GE: return LT;
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case LT: return GE;
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case GT: return LE;
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case LE: return GT;
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}
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}
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} // namespace ARMCC
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inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case ARMCC::EQ: return "eq";
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case ARMCC::NE: return "ne";
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case ARMCC::HS: return "hs";
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case ARMCC::LO: return "lo";
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case ARMCC::MI: return "mi";
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case ARMCC::PL: return "pl";
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case ARMCC::VS: return "vs";
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case ARMCC::VC: return "vc";
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case ARMCC::HI: return "hi";
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case ARMCC::LS: return "ls";
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case ARMCC::GE: return "ge";
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case ARMCC::LT: return "lt";
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case ARMCC::GT: return "gt";
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case ARMCC::LE: return "le";
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case ARMCC::AL: return "al";
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}
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}
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/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model
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/// operations involving sub-registers.
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bool ModelWithRegSequence();
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FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
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JITCodeEmitter &JCE);
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FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
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FunctionPass *createARMExpandPseudoPass();
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FunctionPass *createARMConstantIslandPass();
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FunctionPass *createNEONPreAllocPass();
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FunctionPass *createNEONMoveFixPass();
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FunctionPass *createThumb2ITBlockPass(bool PreAlloc = false);
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FunctionPass *createThumb2SizeReductionPass();
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extern Target TheARMTarget, TheThumbTarget;
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} // end namespace llvm;
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// Defines symbolic names for ARM registers. This defines a mapping from
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// register name to register number.
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//
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#include "ARMGenRegisterNames.inc"
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// Defines symbolic names for the ARM instructions.
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//
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#include "ARMGenInstrNames.inc"
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#endif
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