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https://github.com/c64scene-ar/llvm-6502.git
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8a8d479214
change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
355 lines
13 KiB
C++
355 lines
13 KiB
C++
//=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsFrameLowering.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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//
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// Stack Frame Processing methods
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// +----------------------------+
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//
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// The stack is allocated decrementing the stack pointer on
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// the first instruction of a function prologue. Once decremented,
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// all stack references are done thought a positive offset
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// from the stack/frame pointer, so the stack is considering
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// to grow up! Otherwise terrible hacks would have to be made
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// to get this stack ABI compliant :)
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//
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// The stack frame required by the ABI (after call):
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// Offset
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//
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// 0 ----------
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// 4 Args to pass
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// . saved $GP (used in PIC)
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// . Alloca allocations
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// . Local Area
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// . CPU "Callee Saved" Registers
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// . saved FP
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// . saved RA
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// . FPU "Callee Saved" Registers
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// StackSize -----------
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//
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// Offset - offset from sp after stack allocation on function prologue
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//
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// The sp is the stack pointer subtracted/added from the stack size
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// at the Prologue/Epilogue
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//
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// References to the previous stack (to obtain arguments) are done
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// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
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//
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// Examples:
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// - reference to the actual stack frame
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// for any local area var there is smt like : FI >= 0, StackOffset: 4
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// sw REGX, 4(SP)
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//
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// - reference to previous stack frame
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// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
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// The emitted instruction will be something like:
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// lw REGX, 16+StackSize(SP)
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//
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// Since the total stack size is unknown on LowerFormalArguments, all
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// stack references (ObjectOffset) created to reference the function
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// arguments, are negative numbers. This way, on eliminateFrameIndex it's
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// possible to detect those references and the offsets are adjusted to
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// their real location.
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//
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
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}
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bool MipsFrameLowering::targetHandlesStackFrameRounding() const {
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return true;
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}
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static unsigned AlignOffset(unsigned Offset, unsigned Align) {
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return (Offset + Align - 1) / Align * Align;
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}
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// expand pair of register and immediate if the immediate doesn't fit in the
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// 16-bit offset field.
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// e.g.
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// if OrigImm = 0x10000, OrigReg = $sp:
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// generate the following sequence of instrs:
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// lui $at, hi(0x10000)
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// addu $at, $sp, $at
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//
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// (NewReg, NewImm) = ($at, lo(Ox10000))
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// return true
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static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm,
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unsigned& NewReg, int& NewImm,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator I) {
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// OrigImm fits in the 16-bit field
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if (OrigImm < 0x8000 && OrigImm >= -0x8000) {
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NewReg = OrigReg;
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NewImm = OrigImm;
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return false;
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}
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MachineFunction* MF = MBB.getParent();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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DebugLoc DL = I->getDebugLoc();
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int ImmLo = (short)(OrigImm & 0xffff);
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int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
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((OrigImm & 0x8000) != 0);
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// FIXME: change this when mips goes MC".
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BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
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BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
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BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
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.addReg(Mips::AT);
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NewReg = Mips::AT;
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NewImm = ImmLo;
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return true;
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}
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void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
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unsigned NewReg = 0;
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int NewImm = 0;
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bool ATUsed;
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unsigned GP = STI.isABI_N64() ? Mips::GP_64 : Mips::GP;
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unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
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// First, compute final stack size.
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unsigned RegSize = STI.isGP32bit() ? 4 : 8;
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unsigned StackAlign = getStackAlignment();
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unsigned LocalVarAreaOffset = MipsFI->needGPSaveRestore() ?
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(MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) :
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MipsFI->getMaxCallFrameSize();
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unsigned StackSize = AlignOffset(LocalVarAreaOffset, StackAlign) +
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AlignOffset(MFI->getStackSize(), StackAlign);
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// Update stack size
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MFI->setStackSize(StackSize);
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
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// Emit instructions that set $gp using the the value of $t9.
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// O32 uses the directive .cpload while N32/64 requires three instructions to
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// do this.
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// TODO: Do not emit these instructions if no instructions use $gp.
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if (isPIC && STI.isABI_O32())
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BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::CPLOAD))
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.addReg(RegInfo->getPICCallReg());
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else if (STI.isABI_N64() || (isPIC && STI.isABI_N32())) {
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// lui $28,%hi(%neg(%gp_rel(fname)))
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// addu $28,$28,$25
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// addiu $28,$28,%lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, MBBI, dl, TII.get(LUi), GP)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), GP).addReg(GP).addReg(T9);
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), GP).addReg(GP)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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}
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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MachineModuleInfo &MMI = MF.getMMI();
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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MachineLocation DstML, SrcML;
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// Adjust stack : addi sp, sp, (-imm)
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ATUsed = expandRegLargeImmPair(SP, -StackSize, NewReg, NewImm, MBB, MBBI);
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(NewReg).addImm(NewImm);
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// FIXME: change this when mips goes MC".
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if (ATUsed)
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
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// emit ".cfi_def_cfa_offset StackSize"
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MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
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DstML = MachineLocation(MachineLocation::VirtualFP);
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SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
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Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.size()) {
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// Find the instruction past the last instruction that saves a callee-saved
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// register to the stack.
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for (unsigned i = 0; i < CSI.size(); ++i)
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++MBBI;
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// Iterate over list of callee-saved registers and emit .cfi_offset
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// directives.
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MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
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unsigned Reg = I->getReg();
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// If Reg is a double precision register, emit two cfa_offsets,
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// one for each of the paired single precision registers.
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if (Mips::AFGR64RegisterClass->contains(Reg)) {
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const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
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MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
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MachineLocation SrcML0(*SubRegs);
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MachineLocation SrcML1(*(SubRegs + 1));
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if (!STI.isLittle())
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std::swap(SrcML0, SrcML1);
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Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
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Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
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}
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else {
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// Reg is either in CPURegs or FGR32.
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DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
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SrcML = MachineLocation(Reg);
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Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
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}
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}
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}
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// if framepointer enabled, set it to point to the stack pointer.
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if (hasFP(MF)) {
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// Insert instruction "move $fp, $sp" at this location.
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
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// emit ".cfi_def_cfa_register $fp"
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MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
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DstML = MachineLocation(FP);
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SrcML = MachineLocation(MachineLocation::VirtualFP);
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Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
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}
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// Restore GP from the saved stack location
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if (MipsFI->needGPSaveRestore()) {
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unsigned Offset = MFI->getObjectOffset(MipsFI->getGPFI());
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BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)).addImm(Offset);
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if (Offset >= 0x8000) {
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BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::MACRO));
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
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}
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}
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}
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void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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// Get the number of bytes from FrameInfo
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unsigned StackSize = MFI->getStackSize();
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unsigned NewReg = 0;
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int NewImm = 0;
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bool ATUsed = false;
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// if framepointer enabled, restore the stack pointer.
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if (hasFP(MF)) {
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// Find the first instruction that restores a callee-saved register.
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MachineBasicBlock::iterator I = MBBI;
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for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
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--I;
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// Insert instruction "move $sp, $fp" at this location.
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BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
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}
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// adjust stack : insert addi sp, sp, (imm)
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if (StackSize) {
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ATUsed = expandRegLargeImmPair(SP, StackSize, NewReg, NewImm, MBB, MBBI);
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(NewReg).addImm(NewImm);
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// FIXME: change this when mips goes MC".
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if (ATUsed)
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
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}
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}
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void MipsFrameLowering::
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processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const {
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MachineRegisterInfo& MRI = MF.getRegInfo();
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unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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// FIXME: remove this code if register allocator can correctly mark
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// $fp and $ra used or unused.
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// Mark $fp and $ra as used or unused.
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if (hasFP(MF))
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MRI.setPhysRegUsed(FP);
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// The register allocator might determine $ra is used after seeing
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// instruction "jr $ra", but we do not want PrologEpilogInserter to insert
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// instructions to save/restore $ra unless there is a function call.
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// To correct this, $ra is explicitly marked unused if there is no
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// function call.
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if (MF.getFrameInfo()->hasCalls())
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MRI.setPhysRegUsed(RA);
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else
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MRI.setPhysRegUnused(RA);
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}
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