llvm-6502

0 Fork 0

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-04-27 04:18:42 +00:00

Files

T

Tom Stellard c64ec2996c Merging r235641:

------------------------------------------------------------------------
r235641 | thomas.stellard | 2015-04-23 16:32:01 -0400 (Thu, 23 Apr 2015) | 9 lines

R600/SI: Fix indirect addressing with a negative constant offset

When the base register index of the vector plus the constant offset
was less than zero, we were passing the wrong base register to the indirect
addressing instruction.

In this case, we need to set the base register to v0 and then add
the computed (negative) index to m0.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236449 91177308-0d34-0410-b5e6-96231b3b80d8

2015-05-04 19:50:13 +00:00

AArch64

Merging r233410:

2015-04-29 00:41:55 +00:00

ARM

Merging r228518:

2015-02-09 02:38:04 +00:00

CPP

…

Generic

CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.

2014-12-19 20:50:07 +00:00