mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-21 00:32:23 +00:00
87773c318f
Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
841 lines
31 KiB
C++
841 lines
31 KiB
C++
//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the functions necessary to decode AArch64 instruction
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// bitpatterns into MCInsts (with the help of TableGenerated information from
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// the instruction definitions).
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-disassembler"
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#include "AArch64.h"
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#include "AArch64RegisterInfo.h"
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#include "AArch64Subtarget.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// AArch64 disassembler for all AArch64 platforms.
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class AArch64Disassembler : public MCDisassembler {
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OwningPtr<const MCRegisterInfo> RegInfo;
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public:
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/// Initializes the disassembler.
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///
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AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
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: MCDisassembler(STI), RegInfo(Info) {
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}
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~AArch64Disassembler() {}
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/// See MCDisassembler.
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DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
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};
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}
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// Forward-declarations used in the auto-generated files.
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static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus
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DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus
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DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
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unsigned RegNo, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeVPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst,
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unsigned RegNo, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
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unsigned OptionHiS,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
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unsigned Imm6Bits,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
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unsigned Imm6Bits,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
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unsigned RmBits,
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uint64_t Address,
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const void *Decoder);
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template<int RegWidth>
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static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
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unsigned FullImm,
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uint64_t Address,
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const void *Decoder);
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template<int RegWidth>
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static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
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unsigned Bits,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
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unsigned ShiftAmount,
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uint64_t Address,
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const void *Decoder);
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template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
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static DecodeStatus
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DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
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unsigned ShiftAmount,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
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unsigned Val,
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uint64_t Address,
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const void *Decoder);
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template<typename SomeNamedImmMapper>
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static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
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unsigned Val,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus
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DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
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llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
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unsigned Val,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
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unsigned Val,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
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unsigned Val,
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uint64_t Address,
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const void *Decoder);
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static bool Check(DecodeStatus &Out, DecodeStatus In);
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#include "AArch64GenDisassemblerTables.inc"
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#include "AArch64GenInstrInfo.inc"
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static bool Check(DecodeStatus &Out, DecodeStatus In) {
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switch (In) {
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case MCDisassembler::Success:
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// Out stays the same.
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return true;
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case MCDisassembler::SoftFail:
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Out = In;
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return true;
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case MCDisassembler::Fail:
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Out = In;
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return false;
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}
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llvm_unreachable("Invalid DecodeStatus!");
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}
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DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &os,
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raw_ostream &cs) const {
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CommentStream = &cs;
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uint8_t bytes[4];
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// We want to read exactly 4 bytes of data.
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if (Region.readBytes(Address, 4, bytes) == -1) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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// Encoded as a small-endian 32-bit word in the stream.
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uint32_t insn = (bytes[3] << 24) |
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(bytes[2] << 16) |
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(bytes[1] << 8) |
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(bytes[0] << 0);
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// Calling the auto-generated decoder function.
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DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
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this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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return result;
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}
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MI.clear();
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Size = 0;
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return MCDisassembler::Fail;
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}
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static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
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const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
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return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
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}
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static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::VPR64RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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uint16_t Register = getReg(Decoder, AArch64::VPR128RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
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unsigned OptionHiS,
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uint64_t Address,
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const void *Decoder) {
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// Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
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// S}. Hence we want to check bit 1.
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if (!(OptionHiS & 2))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateImm(OptionHiS));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
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unsigned Imm6Bits,
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uint64_t Address,
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const void *Decoder) {
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// In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
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// between 0 and 31.
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if (Imm6Bits > 31)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
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unsigned Imm6Bits,
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uint64_t Address,
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const void *Decoder) {
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// 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
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if (Imm6Bits < 32)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
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unsigned RmBits,
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uint64_t Address,
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const void *Decoder) {
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// Any bits are valid in the instruction (they're architecturally ignored),
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// but a code generator should insert 0.
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Inst.addOperand(MCOperand::CreateImm(0));
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return MCDisassembler::Success;
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}
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template<int RegWidth>
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static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
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unsigned FullImm,
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uint64_t Address,
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const void *Decoder) {
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unsigned Imm16 = FullImm & 0xffff;
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unsigned Shift = FullImm >> 16;
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if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateImm(Imm16));
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Inst.addOperand(MCOperand::CreateImm(Shift));
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return MCDisassembler::Success;
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}
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template<int RegWidth>
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static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
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unsigned Bits,
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uint64_t Address,
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const void *Decoder) {
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uint64_t Imm;
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if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateImm(Bits));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
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unsigned ShiftAmount,
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uint64_t Address,
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const void *Decoder) {
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// Only values 0-4 are valid for this 3-bit field
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if (ShiftAmount > 4)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
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return MCDisassembler::Success;
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}
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static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
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unsigned ShiftAmount,
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uint64_t Address,
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const void *Decoder) {
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// Only values below 32 are valid for a 32-bit register
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if (ShiftAmount > 31)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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unsigned Rd = fieldFromInstruction(Insn, 0, 5);
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unsigned Rn = fieldFromInstruction(Insn, 5, 5);
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unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
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unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
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unsigned SF = fieldFromInstruction(Insn, 31, 1);
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// Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
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// out assertions that it thinks should never be hit.
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enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
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Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
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if (!SF) {
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// ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
|
|
if (ImmR > 31 || ImmS > 31)
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
if (SF) {
|
|
DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
|
|
// BFM MCInsts use Rd as a source too.
|
|
if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
|
|
DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
|
|
} else {
|
|
DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
|
|
// BFM MCInsts use Rd as a source too.
|
|
if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
|
|
DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
|
|
}
|
|
|
|
// ASR and LSR have more specific patterns so they won't get here:
|
|
assert(!(ImmS == 31 && !SF && Opc != BFM)
|
|
&& "shift should have used auto decode");
|
|
assert(!(ImmS == 63 && SF && Opc != BFM)
|
|
&& "shift should have used auto decode");
|
|
|
|
// Extension instructions similarly:
|
|
if (Opc == SBFM && ImmR == 0) {
|
|
assert((ImmS != 7 && ImmS != 15) && "extension got here");
|
|
assert((ImmS != 31 || SF == 0) && "extension got here");
|
|
} else if (Opc == UBFM && ImmR == 0) {
|
|
assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
|
|
}
|
|
|
|
if (Opc == UBFM) {
|
|
// It might be a LSL instruction, which actually takes the shift amount
|
|
// itself as an MCInst operand.
|
|
if (SF && (ImmS + 1) % 64 == ImmR) {
|
|
Inst.setOpcode(AArch64::LSLxxi);
|
|
Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
|
|
return MCDisassembler::Success;
|
|
} else if (!SF && (ImmS + 1) % 32 == ImmR) {
|
|
Inst.setOpcode(AArch64::LSLwwi);
|
|
Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
|
|
return MCDisassembler::Success;
|
|
}
|
|
}
|
|
|
|
// Otherwise it's definitely either an extract or an insert depending on which
|
|
// of ImmR or ImmS is larger.
|
|
unsigned ExtractOp, InsertOp;
|
|
switch (Opc) {
|
|
default: llvm_unreachable("unexpected instruction trying to decode bitfield");
|
|
case SBFM:
|
|
ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
|
|
InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
|
|
break;
|
|
case BFM:
|
|
ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
|
|
InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
|
|
break;
|
|
case UBFM:
|
|
ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
|
|
InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
|
|
break;
|
|
}
|
|
|
|
// Otherwise it's a boring insert or extract
|
|
Inst.addOperand(MCOperand::CreateImm(ImmR));
|
|
Inst.addOperand(MCOperand::CreateImm(ImmS));
|
|
|
|
|
|
if (ImmS < ImmR)
|
|
Inst.setOpcode(InsertOp);
|
|
else
|
|
Inst.setOpcode(ExtractOp);
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
// This decoder exists to add the dummy Lane operand to the MCInst, which must
|
|
// be 1 in assembly but has no other real manifestation.
|
|
unsigned Rd = fieldFromInstruction(Insn, 0, 5);
|
|
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
|
|
unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
|
|
|
|
if (IsToVec) {
|
|
DecodeVPR128RegisterClass(Inst, Rd, Address, Decoder);
|
|
DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
|
|
} else {
|
|
DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
|
|
DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
|
|
}
|
|
|
|
// Add the lane
|
|
Inst.addOperand(MCOperand::CreateImm(1));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
|
|
static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
DecodeStatus Result = MCDisassembler::Success;
|
|
unsigned Rt = fieldFromInstruction(Insn, 0, 5);
|
|
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
|
|
unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
|
|
unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
|
|
unsigned L = fieldFromInstruction(Insn, 22, 1);
|
|
unsigned V = fieldFromInstruction(Insn, 26, 1);
|
|
unsigned Opc = fieldFromInstruction(Insn, 30, 2);
|
|
|
|
// Not an official name, but it turns out that bit 23 distinguishes indexed
|
|
// from non-indexed operations.
|
|
unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
|
|
|
|
if (Indexed && L == 0) {
|
|
// The MCInst for an indexed store has an out operand and 4 ins:
|
|
// Rn_wb, Rt, Rt2, Rn, Imm
|
|
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
|
}
|
|
|
|
// You shouldn't load to the same register twice in an instruction...
|
|
if (L && Rt == Rt2)
|
|
Result = MCDisassembler::SoftFail;
|
|
|
|
// ... or do any operation that writes-back to a transfer register. But note
|
|
// that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
|
|
if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
|
|
Result = MCDisassembler::SoftFail;
|
|
|
|
// Exactly how we decode the MCInst's registers depends on the Opc and V
|
|
// fields of the instruction. These also obviously determine the size of the
|
|
// operation so we can fill in that information while we're at it.
|
|
if (V) {
|
|
// The instruction operates on the FP/SIMD registers
|
|
switch (Opc) {
|
|
default: return MCDisassembler::Fail;
|
|
case 0:
|
|
DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
|
|
DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
|
|
break;
|
|
case 1:
|
|
DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
|
|
DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
|
|
break;
|
|
case 2:
|
|
DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
|
|
DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
|
|
break;
|
|
}
|
|
} else {
|
|
switch (Opc) {
|
|
default: return MCDisassembler::Fail;
|
|
case 0:
|
|
DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
|
|
DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
|
|
break;
|
|
case 1:
|
|
assert(L && "unexpected \"store signed\" attempt");
|
|
DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
|
|
DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
|
|
break;
|
|
case 2:
|
|
DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
|
|
DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (Indexed && L == 1) {
|
|
// The MCInst for an indexed load has 3 out operands and an 3 ins:
|
|
// Rt, Rt2, Rn_wb, Rt2, Rn, Imm
|
|
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
|
}
|
|
|
|
|
|
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
|
Inst.addOperand(MCOperand::CreateImm(SImm7));
|
|
|
|
return Result;
|
|
}
|
|
|
|
static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
|
|
uint32_t Val,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Rt = fieldFromInstruction(Val, 0, 5);
|
|
unsigned Rn = fieldFromInstruction(Val, 5, 5);
|
|
unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
|
|
unsigned MemSize = fieldFromInstruction(Val, 30, 2);
|
|
|
|
DecodeStatus S = MCDisassembler::Success;
|
|
if (Rt == Rt2) S = MCDisassembler::SoftFail;
|
|
|
|
switch (MemSize) {
|
|
case 2:
|
|
if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
|
|
return MCDisassembler::Fail;
|
|
if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
|
|
return MCDisassembler::Fail;
|
|
break;
|
|
case 3:
|
|
if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
|
|
return MCDisassembler::Fail;
|
|
if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
|
|
return MCDisassembler::Fail;
|
|
break;
|
|
default:
|
|
llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
|
|
}
|
|
|
|
if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
|
|
return MCDisassembler::Fail;
|
|
|
|
return S;
|
|
}
|
|
|
|
template<typename SomeNamedImmMapper>
|
|
static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
|
|
unsigned Val,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
SomeNamedImmMapper Mapper;
|
|
bool ValidNamed;
|
|
Mapper.toString(Val, ValidNamed);
|
|
if (ValidNamed || Mapper.validImm(Val)) {
|
|
Inst.addOperand(MCOperand::CreateImm(Val));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
|
|
llvm::MCInst &Inst,
|
|
unsigned Val,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
bool ValidNamed;
|
|
Mapper.toString(Val, ValidNamed);
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(Val));
|
|
|
|
return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
|
|
}
|
|
|
|
static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
|
|
unsigned Val,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
|
|
Decoder);
|
|
}
|
|
|
|
static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
|
|
unsigned Val,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
|
|
Decoder);
|
|
}
|
|
|
|
static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned Rt = fieldFromInstruction(Insn, 0, 5);
|
|
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
|
|
unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
|
|
|
|
unsigned Opc = fieldFromInstruction(Insn, 22, 2);
|
|
unsigned V = fieldFromInstruction(Insn, 26, 1);
|
|
unsigned Size = fieldFromInstruction(Insn, 30, 2);
|
|
|
|
if (Opc == 0 || (V == 1 && Opc == 2)) {
|
|
// It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
|
|
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
|
}
|
|
|
|
if (V == 0 && (Opc == 2 || Size == 3)) {
|
|
DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
|
|
} else if (V == 0) {
|
|
DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
|
|
} else if (V == 1 && (Opc & 2)) {
|
|
DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
|
|
} else {
|
|
switch (Size) {
|
|
case 0:
|
|
DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
|
|
break;
|
|
case 1:
|
|
DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
|
|
break;
|
|
case 2:
|
|
DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
|
|
break;
|
|
case 3:
|
|
DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (Opc != 0 && (V != 1 || Opc != 2)) {
|
|
// It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
|
|
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
|
}
|
|
|
|
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(Imm9));
|
|
|
|
// N.b. The official documentation says undpredictable if Rt == Rn, but this
|
|
// takes place at the architectural rather than encoding level:
|
|
//
|
|
// "STR xzr, [sp], #4" is perfectly valid.
|
|
if (V == 0 && Rt == Rn && Rn != 31)
|
|
return MCDisassembler::SoftFail;
|
|
else
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static MCDisassembler *createAArch64Disassembler(const Target &T,
|
|
const MCSubtargetInfo &STI) {
|
|
return new AArch64Disassembler(STI, T.createMCRegInfo(""));
|
|
}
|
|
|
|
extern "C" void LLVMInitializeAArch64Disassembler() {
|
|
TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
|
|
createAArch64Disassembler);
|
|
}
|
|
|
|
template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
|
|
static DecodeStatus
|
|
DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
|
|
uint64_t Address, const void *Decoder) {
|
|
bool IsLSL = false;
|
|
if (Ext == A64SE::LSL)
|
|
IsLSL = true;
|
|
else if (Ext != A64SE::MSL)
|
|
return MCDisassembler::Fail;
|
|
|
|
// MSL and LSLH accepts encoded shift amount 0 or 1.
|
|
if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
|
|
return MCDisassembler::Fail;
|
|
|
|
// LSL accepts encoded shift amount 0, 1, 2 or 3.
|
|
if (IsLSL && ShiftAmount > 3)
|
|
return MCDisassembler::Fail;
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
|
|
return MCDisassembler::Success;
|
|
}
|