llvm-6502/lib/Target/Alpha
2009-03-29 17:14:14 +00:00
..
AsmPrinter CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. 2009-03-25 01:47:28 +00:00
Alpha.h CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. 2009-03-25 01:47:28 +00:00
Alpha.td
AlphaBranchSelector.cpp
AlphaCodeEmitter.cpp
AlphaInstrFormats.td
AlphaInstrInfo.cpp Factor out the code to add a MachineOperand to a MachineInstrBuilder. 2009-02-18 05:45:50 +00:00
AlphaInstrInfo.h Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty 2009-02-09 07:14:22 +00:00
AlphaInstrInfo.td Add support to tablegen for naming the nodes themselves, not just the operands, 2009-03-19 05:21:56 +00:00
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp Remove non-DebugLoc versions of BuildMI from Alpha and Cell. 2009-02-13 02:30:42 +00:00
AlphaISelLowering.h Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing 2009-02-07 16:15:20 +00:00
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp Remove non-DebugLoc versions of BuildMI from Alpha and Cell. 2009-02-13 02:30:42 +00:00
AlphaRegisterInfo.cpp Propagate debug loc info through prologue/epilogue. 2009-02-23 00:42:30 +00:00
AlphaRegisterInfo.h
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetAsmInfo.cpp Alpha always requires global relocations to be r/w regardless of PIC. 2009-03-29 17:14:14 +00:00
AlphaTargetAsmInfo.h Alpha always requires global relocations to be r/w regardless of PIC. 2009-03-29 17:14:14 +00:00
AlphaTargetMachine.cpp CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. 2009-03-25 01:47:28 +00:00
AlphaTargetMachine.h CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. 2009-03-25 01:47:28 +00:00
CMakeLists.txt
Makefile
README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html