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https://github.com/c64scene-ar/llvm-6502.git
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9f44b3a411
* remove some old code that was needed when we'd put ESP in the scale instead of the base of some instructions. * Fix a bug with the P modifier in inline asm that caused us to drop it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75077 91177308-0d34-0410-b5e6-96231b3b80d8
51 lines
1.5 KiB
LLVM
51 lines
1.5 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86-64 | FileCheck %s -check-prefix=CHECK-64
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; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin9 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-32
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; PR3379
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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@per_cpu__cpu_number = external global i32 ; <i32*> [#uses=1]
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declare void @bar(...)
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define i32 @test1() nounwind {
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entry:
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; Should have a rip suffix.
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; CHECK-64: test1:
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; CHECK-64: movl %gs:per_cpu__cpu_number(%rip),%eax
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; CHECK-32: test1:
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; CHECK-32: movl %gs:(%eax),%eax
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%A = call i32 asm "movl %gs:$1,$0",
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"=r,*m"(i32* @per_cpu__cpu_number) nounwind
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ret i32 %A
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}
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define i32 @test2() nounwind {
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entry:
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; Should not have a rip suffix because of the P modifier.
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; CHECK-64: test2:
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; CHECK-64: movl %gs:per_cpu__cpu_number,%eax
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; CHECK-32: test2:
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; CHECK-32: movl %gs:(%eax),%eax
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%A = call i32 asm "movl %gs:${1:P},$0",
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"=r,*m"(i32* @per_cpu__cpu_number) nounwind
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ret i32 %A
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}
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define void @test3() nounwind {
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entry:
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; CHECK-64: test3:
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; CHECK-64: call bar
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; CHECK-64: call test3
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; CHECK-32: test3:
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; CHECK-32: call _bar
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; CHECK-32: call _test3
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tail call void asm sideeffect "call ${0:P}", "X"(void (...)* @bar) nounwind
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tail call void asm sideeffect "call ${0:P}", "X"(void (...)* bitcast (void ()* @test3 to void (...)*)) nounwind
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ret void
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}
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