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https://github.com/c64scene-ar/llvm-6502.git
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b7927f100d
Adding test to show correct instruction selection and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222249 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
4.0 KiB
C++
115 lines
4.0 KiB
C++
//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/LEB128.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/Endian.h"
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#include <vector>
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#include <array>
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using namespace llvm;
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#define DEBUG_TYPE "hexagon-disassembler"
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// Pull DecodeStatus and its enum values into the global namespace.
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typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// \brief Hexagon disassembler for all Hexagon platforms.
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class HexagonDisassembler : public MCDisassembler {
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public:
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HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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}
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static const uint16_t IntRegDecoderTable[] = {
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Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
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Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
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Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
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Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
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Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
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Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
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Hexagon::R30, Hexagon::R31 };
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static const uint16_t PredRegDecoderTable[] = { Hexagon::P0, Hexagon::P1,
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Hexagon::P2, Hexagon::P3 };
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/,
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void const *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Register = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/,
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void const *Decoder) {
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if (RegNo > 3)
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return MCDisassembler::Fail;
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unsigned Register = PredRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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#include "HexagonGenDisassemblerTables.inc"
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static MCDisassembler *createHexagonDisassembler(Target const &T,
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MCSubtargetInfo const &STI,
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MCContext &Ctx) {
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return new HexagonDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeHexagonDisassembler() {
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TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
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createHexagonDisassembler);
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}
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DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &os,
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raw_ostream &cs) const {
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Size = 4;
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if (Bytes.size() < 4)
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return MCDisassembler::Fail;
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uint32_t insn =
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llvm::support::endian::read<uint32_t, llvm::support::little,
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llvm::support::unaligned>(Bytes.data());
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// Remove parse bits.
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insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK);
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return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
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}
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