mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c6deb3d447
it as a late BURR scheduling tie-breaker. Intuitively, it's good to push down instructions whose results are liveout so their long live ranges won't conflict with other values which are needed inside the BB. Further prioritize liveout instructions by the number of operands which are calculated within the BB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35109 91177308-0d34-0410-b5e6-96231b3b80d8
946 lines
31 KiB
C++
946 lines
31 KiB
C++
//===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Evan Cheng and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements bottom-up and top-down register pressure reduction list
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// schedulers, using standard algorithms. The basic approach uses a priority
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// queue of available nodes to schedule. One at a time, nodes are taken from
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// the priority queue (thus in priority order), checked for legality to
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// schedule, and emitted if legal.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/ADT/Statistic.h"
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#include <climits>
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#include <queue>
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static RegisterScheduler
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burrListDAGScheduler("list-burr",
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" Bottom-up register reduction list scheduling",
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createBURRListDAGScheduler);
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static RegisterScheduler
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tdrListrDAGScheduler("list-tdrr",
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" Top-down register reduction list scheduling",
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createTDRRListDAGScheduler);
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namespace {
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//===----------------------------------------------------------------------===//
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/// ScheduleDAGRRList - The actual register reduction list scheduler
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/// implementation. This supports both top-down and bottom-up scheduling.
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///
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class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
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private:
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/// isBottomUp - This is true if the scheduling problem is bottom-up, false if
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/// it is top-down.
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bool isBottomUp;
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/// AvailableQueue - The priority queue to use for the available SUnits.
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///
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SchedulingPriorityQueue *AvailableQueue;
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public:
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ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm, bool isbottomup,
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SchedulingPriorityQueue *availqueue)
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: ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup),
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AvailableQueue(availqueue) {
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}
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~ScheduleDAGRRList() {
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delete AvailableQueue;
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}
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void Schedule();
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private:
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void ReleasePred(SUnit *PredSU, bool isChain, unsigned CurCycle);
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void ReleaseSucc(SUnit *SuccSU, bool isChain, unsigned CurCycle);
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void ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle);
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void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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void ListScheduleTopDown();
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void ListScheduleBottomUp();
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void CommuteNodesToReducePressure();
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};
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} // end anonymous namespace
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/// Schedule - Schedule the DAG using list scheduling.
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void ScheduleDAGRRList::Schedule() {
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DOUT << "********** List Scheduling **********\n";
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// Build scheduling units.
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BuildSchedUnits();
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(&DAG));
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CalculateDepths();
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CalculateHeights();
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AvailableQueue->initNodes(SUnitMap, SUnits);
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// Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
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if (isBottomUp)
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ListScheduleBottomUp();
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else
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ListScheduleTopDown();
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AvailableQueue->releaseState();
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CommuteNodesToReducePressure();
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DOUT << "*** Final schedule ***\n";
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DEBUG(dumpSchedule());
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DOUT << "\n";
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// Emit in scheduled order
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EmitSchedule();
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}
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/// CommuteNodesToReducePressure - If a node is two-address and commutable, and
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/// it is not the last use of its first operand, add it to the CommuteSet if
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/// possible. It will be commuted when it is translated to a MI.
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void ScheduleDAGRRList::CommuteNodesToReducePressure() {
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std::set<SUnit *> OperandSeen;
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for (unsigned i = Sequence.size()-1; i != 0; --i) { // Ignore first node.
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SUnit *SU = Sequence[i];
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if (!SU) continue;
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if (SU->isCommutable) {
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unsigned Opc = SU->Node->getTargetOpcode();
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unsigned NumRes = CountResults(SU->Node);
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unsigned NumOps = CountOperands(SU->Node);
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for (unsigned j = 0; j != NumOps; ++j) {
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if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
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continue;
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SDNode *OpN = SU->Node->getOperand(j).Val;
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SUnit *OpSU = SUnitMap[OpN];
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if (OpSU && OperandSeen.count(OpSU) == 1) {
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// Ok, so SU is not the last use of OpSU, but SU is two-address so
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// it will clobber OpSU. Try to commute SU if no other source operands
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// are live below.
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bool DoCommute = true;
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for (unsigned k = 0; k < NumOps; ++k) {
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if (k != j) {
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OpN = SU->Node->getOperand(k).Val;
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OpSU = SUnitMap[OpN];
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if (OpSU && OperandSeen.count(OpSU) == 1) {
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DoCommute = false;
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break;
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}
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}
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}
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if (DoCommute)
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CommuteSet.insert(SU->Node);
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}
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// Only look at the first use&def node for now.
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break;
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}
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}
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (!I->second)
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OperandSeen.insert(I->first);
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// Bottom-Up Scheduling
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//===----------------------------------------------------------------------===//
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// the Available queue is the count reaches zero. Also update its cycle bound.
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void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
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unsigned CurCycle) {
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// FIXME: the distance between two nodes is not always == the predecessor's
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
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if (!isChain)
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PredSU->NumSuccsLeft--;
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else
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PredSU->NumChainSuccsLeft--;
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#ifndef NDEBUG
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if (PredSU->NumSuccsLeft < 0 || PredSU->NumChainSuccsLeft < 0) {
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cerr << "*** List scheduling failed! ***\n";
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PredSU->dump(&DAG);
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cerr << " has been released too many times!\n";
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assert(0);
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}
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#endif
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if ((PredSU->NumSuccsLeft + PredSU->NumChainSuccsLeft) == 0) {
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// EntryToken has to go last! Special case it here.
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if (PredSU->Node->getOpcode() != ISD::EntryToken) {
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PredSU->isAvailable = true;
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AvailableQueue->push(PredSU);
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}
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}
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}
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/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
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/// count of its predecessors. If a predecessor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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DOUT << "*** Scheduling [" << CurCycle << "]: ";
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DEBUG(SU->dump(&DAG));
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SU->Cycle = CurCycle;
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AvailableQueue->ScheduledNode(SU);
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Sequence.push_back(SU);
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// Bottom up: release predecessors
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I)
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ReleasePred(I->first, I->second, CurCycle);
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SU->isScheduled = true;
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}
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/// isReady - True if node's lower cycle bound is less or equal to the current
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/// scheduling cycle. Always true if all nodes have uniform latency 1.
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static inline bool isReady(SUnit *SU, unsigned CurCycle) {
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return SU->CycleBound <= CurCycle;
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}
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/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
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/// schedulers.
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void ScheduleDAGRRList::ListScheduleBottomUp() {
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unsigned CurCycle = 0;
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// Add root to Available queue.
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AvailableQueue->push(SUnitMap[DAG.getRoot().Val]);
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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std::vector<SUnit*> NotReady;
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while (!AvailableQueue->empty()) {
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SUnit *CurNode = AvailableQueue->pop();
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while (CurNode && !isReady(CurNode, CurCycle)) {
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NotReady.push_back(CurNode);
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CurNode = AvailableQueue->pop();
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}
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// Add the nodes that aren't ready back onto the available list.
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AvailableQueue->push_all(NotReady);
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NotReady.clear();
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if (CurNode != NULL)
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ScheduleNodeBottomUp(CurNode, CurCycle);
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CurCycle++;
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}
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// Add entry node last
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if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
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SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
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Sequence.push_back(Entry);
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}
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// Reverse the order if it is bottom up.
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std::reverse(Sequence.begin(), Sequence.end());
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#ifndef NDEBUG
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// Verify that all SUnits were scheduled.
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bool AnyNotSched = false;
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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if (SUnits[i].NumSuccsLeft != 0 || SUnits[i].NumChainSuccsLeft != 0) {
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if (!AnyNotSched)
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cerr << "*** List scheduling failed! ***\n";
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SUnits[i].dump(&DAG);
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cerr << "has not been scheduled!\n";
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AnyNotSched = true;
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}
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}
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assert(!AnyNotSched);
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#endif
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}
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//===----------------------------------------------------------------------===//
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// Top-Down Scheduling
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//===----------------------------------------------------------------------===//
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
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/// the PendingQueue if the count reaches zero.
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void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
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unsigned CurCycle) {
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// FIXME: the distance between two nodes is not always == the predecessor's
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency);
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if (!isChain)
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SuccSU->NumPredsLeft--;
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else
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SuccSU->NumChainPredsLeft--;
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#ifndef NDEBUG
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if (SuccSU->NumPredsLeft < 0 || SuccSU->NumChainPredsLeft < 0) {
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cerr << "*** List scheduling failed! ***\n";
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SuccSU->dump(&DAG);
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cerr << " has been released too many times!\n";
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assert(0);
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}
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#endif
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if ((SuccSU->NumPredsLeft + SuccSU->NumChainPredsLeft) == 0) {
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SuccSU->isAvailable = true;
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AvailableQueue->push(SuccSU);
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}
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}
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/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
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/// count of its successors. If a successor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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DOUT << "*** Scheduling [" << CurCycle << "]: ";
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DEBUG(SU->dump(&DAG));
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SU->Cycle = CurCycle;
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AvailableQueue->ScheduledNode(SU);
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Sequence.push_back(SU);
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// Top down: release successors
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I)
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ReleaseSucc(I->first, I->second, CurCycle);
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SU->isScheduled = true;
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}
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void ScheduleDAGRRList::ListScheduleTopDown() {
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unsigned CurCycle = 0;
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SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
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// All leaves to Available queue.
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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// It is available if it has no predecessors.
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if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
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AvailableQueue->push(&SUnits[i]);
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SUnits[i].isAvailable = true;
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}
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}
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// Emit the entry node first.
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ScheduleNodeTopDown(Entry, CurCycle);
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CurCycle++;
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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std::vector<SUnit*> NotReady;
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while (!AvailableQueue->empty()) {
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SUnit *CurNode = AvailableQueue->pop();
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while (CurNode && !isReady(CurNode, CurCycle)) {
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NotReady.push_back(CurNode);
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CurNode = AvailableQueue->pop();
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}
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// Add the nodes that aren't ready back onto the available list.
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AvailableQueue->push_all(NotReady);
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NotReady.clear();
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if (CurNode != NULL)
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ScheduleNodeTopDown(CurNode, CurCycle);
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CurCycle++;
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}
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#ifndef NDEBUG
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// Verify that all SUnits were scheduled.
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bool AnyNotSched = false;
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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if (!SUnits[i].isScheduled) {
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if (!AnyNotSched)
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cerr << "*** List scheduling failed! ***\n";
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SUnits[i].dump(&DAG);
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cerr << "has not been scheduled!\n";
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AnyNotSched = true;
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}
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}
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assert(!AnyNotSched);
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#endif
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}
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//===----------------------------------------------------------------------===//
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// RegReductionPriorityQueue Implementation
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//===----------------------------------------------------------------------===//
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//
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// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
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// to reduce register pressure.
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//
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namespace {
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template<class SF>
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class RegReductionPriorityQueue;
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/// Sorting functions for the Available queue.
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struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
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RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
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bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
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bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
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bool operator()(const SUnit* left, const SUnit* right) const;
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};
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struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
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RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
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td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
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td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
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bool operator()(const SUnit* left, const SUnit* right) const;
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};
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} // end anonymous namespace
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static inline bool isCopyFromLiveIn(const SUnit *SU) {
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SDNode *N = SU->Node;
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return N->getOpcode() == ISD::CopyFromReg &&
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N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
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}
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namespace {
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template<class SF>
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class VISIBILITY_HIDDEN RegReductionPriorityQueue
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: public SchedulingPriorityQueue {
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std::priority_queue<SUnit*, std::vector<SUnit*>, SF> Queue;
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public:
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RegReductionPriorityQueue() :
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Queue(SF(this)) {}
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virtual void initNodes(DenseMap<SDNode*, SUnit*> &sumap,
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std::vector<SUnit> &sunits) {}
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virtual void releaseState() {}
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virtual unsigned getNodePriority(const SUnit *SU) const {
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return 0;
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}
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bool empty() const { return Queue.empty(); }
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void push(SUnit *U) {
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Queue.push(U);
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}
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void push_all(const std::vector<SUnit *> &Nodes) {
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for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
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Queue.push(Nodes[i]);
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}
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SUnit *pop() {
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if (empty()) return NULL;
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SUnit *V = Queue.top();
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Queue.pop();
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return V;
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}
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virtual bool isDUOperand(const SUnit *SU1, const SUnit *SU2) {
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return false;
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}
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};
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template<class SF>
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class VISIBILITY_HIDDEN BURegReductionPriorityQueue
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: public RegReductionPriorityQueue<SF> {
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// SUnitMap SDNode to SUnit mapping (n -> 1).
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DenseMap<SDNode*, SUnit*> *SUnitMap;
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// SUnits - The SUnits for the current graph.
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const std::vector<SUnit> *SUnits;
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// SethiUllmanNumbers - The SethiUllman number for each node.
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std::vector<unsigned> SethiUllmanNumbers;
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const TargetInstrInfo *TII;
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public:
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BURegReductionPriorityQueue(const TargetInstrInfo *tii)
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: TII(tii) {}
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void initNodes(DenseMap<SDNode*, SUnit*> &sumap,
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std::vector<SUnit> &sunits) {
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SUnitMap = &sumap;
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SUnits = &sunits;
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// Add pseudo dependency edges for two-address nodes.
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AddPseudoTwoAddrDeps();
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// Calculate node priorities.
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CalculateSethiUllmanNumbers();
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}
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void releaseState() {
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SUnits = 0;
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SethiUllmanNumbers.clear();
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}
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unsigned getNodePriority(const SUnit *SU) const {
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assert(SU->NodeNum < SethiUllmanNumbers.size());
|
|
unsigned Opc = SU->Node->getOpcode();
|
|
if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU))
|
|
// CopyFromReg should be close to its def because it restricts
|
|
// allocation choices. But if it is a livein then perhaps we want it
|
|
// closer to its uses so it can be coalesced.
|
|
return 0xffff;
|
|
else if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
|
|
// CopyToReg should be close to its uses to facilitate coalescing and
|
|
// avoid spilling.
|
|
return 0;
|
|
else if (SU->NumSuccs == 0)
|
|
// If SU does not have a use, i.e. it doesn't produce a value that would
|
|
// be consumed (e.g. store), then it terminates a chain of computation.
|
|
// Give it a large SethiUllman number so it will be scheduled right
|
|
// before its predecessors that it doesn't lengthen their live ranges.
|
|
return 0xffff;
|
|
else if (SU->NumPreds == 0)
|
|
// If SU does not have a def, schedule it close to its uses because it
|
|
// does not lengthen any live ranges.
|
|
return 0;
|
|
else
|
|
return SethiUllmanNumbers[SU->NodeNum];
|
|
}
|
|
|
|
bool isDUOperand(const SUnit *SU1, const SUnit *SU2) {
|
|
unsigned Opc = SU1->Node->getTargetOpcode();
|
|
unsigned NumRes = ScheduleDAG::CountResults(SU1->Node);
|
|
unsigned NumOps = ScheduleDAG::CountOperands(SU1->Node);
|
|
for (unsigned i = 0; i != NumOps; ++i) {
|
|
if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) == -1)
|
|
continue;
|
|
if (SU1->Node->getOperand(i).isOperand(SU2->Node))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
private:
|
|
bool canClobber(SUnit *SU, SUnit *Op);
|
|
void AddPseudoTwoAddrDeps();
|
|
void CalculateSethiUllmanNumbers();
|
|
unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
|
|
};
|
|
|
|
|
|
template<class SF>
|
|
class TDRegReductionPriorityQueue : public RegReductionPriorityQueue<SF> {
|
|
// SUnitMap SDNode to SUnit mapping (n -> 1).
|
|
DenseMap<SDNode*, SUnit*> *SUnitMap;
|
|
|
|
// SUnits - The SUnits for the current graph.
|
|
const std::vector<SUnit> *SUnits;
|
|
|
|
// SethiUllmanNumbers - The SethiUllman number for each node.
|
|
std::vector<unsigned> SethiUllmanNumbers;
|
|
|
|
public:
|
|
TDRegReductionPriorityQueue() {}
|
|
|
|
void initNodes(DenseMap<SDNode*, SUnit*> &sumap,
|
|
std::vector<SUnit> &sunits) {
|
|
SUnitMap = &sumap;
|
|
SUnits = &sunits;
|
|
// Calculate node priorities.
|
|
CalculateSethiUllmanNumbers();
|
|
}
|
|
|
|
void releaseState() {
|
|
SUnits = 0;
|
|
SethiUllmanNumbers.clear();
|
|
}
|
|
|
|
unsigned getNodePriority(const SUnit *SU) const {
|
|
assert(SU->NodeNum < SethiUllmanNumbers.size());
|
|
return SethiUllmanNumbers[SU->NodeNum];
|
|
}
|
|
|
|
private:
|
|
void CalculateSethiUllmanNumbers();
|
|
unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
|
|
};
|
|
}
|
|
|
|
/// closestSucc - Returns the scheduled cycle of the successor which is
|
|
/// closet to the current cycle.
|
|
static unsigned closestSucc(const SUnit *SU) {
|
|
unsigned MaxCycle = 0;
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
unsigned Cycle = I->first->Cycle;
|
|
// If there are bunch of CopyToRegs stacked up, they should be considered
|
|
// to be at the same position.
|
|
if (I->first->Node->getOpcode() == ISD::CopyToReg)
|
|
Cycle = closestSucc(I->first)+1;
|
|
if (Cycle > MaxCycle)
|
|
MaxCycle = Cycle;
|
|
}
|
|
return MaxCycle;
|
|
}
|
|
|
|
/// calcMaxScratches - Returns an cost estimate of the worse case requirement
|
|
/// for scratch registers. Live-in operands and live-out results don't count
|
|
/// since they are "fixed".
|
|
static unsigned calcMaxScratches(const SUnit *SU) {
|
|
unsigned Scratches = 0;
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue; // ignore chain preds
|
|
if (I->first->Node->getOpcode() != ISD::CopyFromReg)
|
|
Scratches++;
|
|
}
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue; // ignore chain succs
|
|
if (I->first->Node->getOpcode() != ISD::CopyToReg)
|
|
Scratches += 10;
|
|
}
|
|
return Scratches;
|
|
}
|
|
|
|
// Bottom up
|
|
bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
|
|
bool LIsTarget = left->Node->isTargetOpcode();
|
|
bool RIsTarget = right->Node->isTargetOpcode();
|
|
|
|
// Special tie breaker: if two nodes share a operand, the one that use it
|
|
// as a def&use operand is preferred.
|
|
if (LIsTarget && RIsTarget) {
|
|
if (left->isTwoAddress && !right->isTwoAddress)
|
|
if (SPQ->isDUOperand(left, right))
|
|
return false;
|
|
if (!left->isTwoAddress && right->isTwoAddress)
|
|
if (SPQ->isDUOperand(right, left))
|
|
return true;
|
|
}
|
|
|
|
unsigned LPriority = SPQ->getNodePriority(left);
|
|
unsigned RPriority = SPQ->getNodePriority(right);
|
|
if (LPriority > RPriority)
|
|
return true;
|
|
else if (LPriority == RPriority) {
|
|
// Try schedule def + use closer whne Sethi-Ullman numbers are the same.
|
|
// e.g.
|
|
// t1 = op t2, c1
|
|
// t3 = op t4, c2
|
|
//
|
|
// and the following instructions are both ready.
|
|
// t2 = op c3
|
|
// t4 = op c4
|
|
//
|
|
// Then schedule t2 = op first.
|
|
// i.e.
|
|
// t4 = op c4
|
|
// t2 = op c3
|
|
// t1 = op t2, c1
|
|
// t3 = op t4, c2
|
|
//
|
|
// This creates more short live intervals.
|
|
unsigned LDist = closestSucc(left);
|
|
unsigned RDist = closestSucc(right);
|
|
if (LDist < RDist)
|
|
return true;
|
|
else if (LDist == RDist) {
|
|
// Intuitively, it's good to push down instructions whose results are
|
|
// liveout so their long live ranges won't conflict with other values
|
|
// which are needed inside the BB. Further prioritize liveout instructions
|
|
// by the number of operands which are calculated within the BB.
|
|
unsigned LScratch = calcMaxScratches(left);
|
|
unsigned RScratch = calcMaxScratches(right);
|
|
if (LScratch > RScratch)
|
|
return true;
|
|
else if (LScratch == RScratch)
|
|
if (left->Height > right->Height)
|
|
return true;
|
|
else if (left->Height == right->Height)
|
|
if (left->Depth < right->Depth)
|
|
return true;
|
|
else if (left->Depth == right->Depth)
|
|
if (left->CycleBound > right->CycleBound)
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// FIXME: This is probably too slow!
|
|
static void isReachable(SUnit *SU, SUnit *TargetSU,
|
|
std::set<SUnit *> &Visited, bool &Reached) {
|
|
if (Reached) return;
|
|
if (SU == TargetSU) {
|
|
Reached = true;
|
|
return;
|
|
}
|
|
if (!Visited.insert(SU).second) return;
|
|
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E;
|
|
++I)
|
|
isReachable(I->first, TargetSU, Visited, Reached);
|
|
}
|
|
|
|
static bool isReachable(SUnit *SU, SUnit *TargetSU) {
|
|
std::set<SUnit *> Visited;
|
|
bool Reached = false;
|
|
isReachable(SU, TargetSU, Visited, Reached);
|
|
return Reached;
|
|
}
|
|
|
|
template<class SF>
|
|
bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
|
|
if (SU->isTwoAddress) {
|
|
unsigned Opc = SU->Node->getTargetOpcode();
|
|
unsigned NumRes = ScheduleDAG::CountResults(SU->Node);
|
|
unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
|
|
for (unsigned i = 0; i != NumOps; ++i) {
|
|
if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
|
|
SDNode *DU = SU->Node->getOperand(i).Val;
|
|
if (Op == (*SUnitMap)[DU])
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
|
|
/// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
|
|
/// it as a def&use operand. Add a pseudo control edge from it to the other
|
|
/// node (if it won't create a cycle) so the two-address one will be scheduled
|
|
/// first (lower in the schedule).
|
|
template<class SF>
|
|
void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
|
|
SUnit *SU = (SUnit *)&((*SUnits)[i]);
|
|
if (!SU->isTwoAddress)
|
|
continue;
|
|
|
|
SDNode *Node = SU->Node;
|
|
if (!Node->isTargetOpcode())
|
|
continue;
|
|
|
|
unsigned Opc = Node->getTargetOpcode();
|
|
unsigned NumRes = ScheduleDAG::CountResults(Node);
|
|
unsigned NumOps = ScheduleDAG::CountOperands(Node);
|
|
for (unsigned j = 0; j != NumOps; ++j) {
|
|
if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {
|
|
SDNode *DU = SU->Node->getOperand(j).Val;
|
|
SUnit *DUSU = (*SUnitMap)[DU];
|
|
if (!DUSU) continue;
|
|
for (SUnit::succ_iterator I = DUSU->Succs.begin(),E = DUSU->Succs.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue;
|
|
SUnit *SuccSU = I->first;
|
|
if (SuccSU != SU &&
|
|
(!canClobber(SuccSU, DUSU) ||
|
|
(!SU->isCommutable && SuccSU->isCommutable))){
|
|
if (SuccSU->Depth == SU->Depth && !isReachable(SuccSU, SU)) {
|
|
DOUT << "Adding an edge from SU # " << SU->NodeNum
|
|
<< " to SU #" << SuccSU->NodeNum << "\n";
|
|
if (SU->addPred(SuccSU, true))
|
|
SU->NumChainPredsLeft++;
|
|
if (SuccSU->addSucc(SU, true))
|
|
SuccSU->NumChainSuccsLeft++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
|
|
/// Smaller number is the higher priority.
|
|
template<class SF>
|
|
unsigned BURegReductionPriorityQueue<SF>::
|
|
CalcNodeSethiUllmanNumber(const SUnit *SU) {
|
|
unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
|
|
if (SethiUllmanNumber != 0)
|
|
return SethiUllmanNumber;
|
|
|
|
unsigned Extra = 0;
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue; // ignore chain preds
|
|
SUnit *PredSU = I->first;
|
|
unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
|
|
if (PredSethiUllman > SethiUllmanNumber) {
|
|
SethiUllmanNumber = PredSethiUllman;
|
|
Extra = 0;
|
|
} else if (PredSethiUllman == SethiUllmanNumber && !I->second)
|
|
Extra++;
|
|
}
|
|
|
|
SethiUllmanNumber += Extra;
|
|
|
|
if (SethiUllmanNumber == 0)
|
|
SethiUllmanNumber = 1;
|
|
|
|
return SethiUllmanNumber;
|
|
}
|
|
|
|
/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
|
|
/// scheduling units.
|
|
template<class SF>
|
|
void BURegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
|
|
SethiUllmanNumbers.assign(SUnits->size(), 0);
|
|
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
|
|
CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
|
|
}
|
|
|
|
static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) {
|
|
unsigned Sum = 0;
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
SUnit *SuccSU = I->first;
|
|
for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
|
|
EE = SuccSU->Preds.end(); II != EE; ++II) {
|
|
SUnit *PredSU = II->first;
|
|
if (!PredSU->isScheduled)
|
|
Sum++;
|
|
}
|
|
}
|
|
|
|
return Sum;
|
|
}
|
|
|
|
|
|
// Top down
|
|
bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
|
|
unsigned LPriority = SPQ->getNodePriority(left);
|
|
unsigned RPriority = SPQ->getNodePriority(right);
|
|
bool LIsTarget = left->Node->isTargetOpcode();
|
|
bool RIsTarget = right->Node->isTargetOpcode();
|
|
bool LIsFloater = LIsTarget && left->NumPreds == 0;
|
|
bool RIsFloater = RIsTarget && right->NumPreds == 0;
|
|
unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0;
|
|
unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0;
|
|
|
|
if (left->NumSuccs == 0 && right->NumSuccs != 0)
|
|
return false;
|
|
else if (left->NumSuccs != 0 && right->NumSuccs == 0)
|
|
return true;
|
|
|
|
// Special tie breaker: if two nodes share a operand, the one that use it
|
|
// as a def&use operand is preferred.
|
|
if (LIsTarget && RIsTarget) {
|
|
if (left->isTwoAddress && !right->isTwoAddress) {
|
|
SDNode *DUNode = left->Node->getOperand(0).Val;
|
|
if (DUNode->isOperand(right->Node))
|
|
RBonus += 2;
|
|
}
|
|
if (!left->isTwoAddress && right->isTwoAddress) {
|
|
SDNode *DUNode = right->Node->getOperand(0).Val;
|
|
if (DUNode->isOperand(left->Node))
|
|
LBonus += 2;
|
|
}
|
|
}
|
|
if (LIsFloater)
|
|
LBonus -= 2;
|
|
if (RIsFloater)
|
|
RBonus -= 2;
|
|
if (left->NumSuccs == 1)
|
|
LBonus += 2;
|
|
if (right->NumSuccs == 1)
|
|
RBonus += 2;
|
|
|
|
if (LPriority+LBonus < RPriority+RBonus)
|
|
return true;
|
|
else if (LPriority == RPriority)
|
|
if (left->Depth < right->Depth)
|
|
return true;
|
|
else if (left->Depth == right->Depth)
|
|
if (left->NumSuccsLeft > right->NumSuccsLeft)
|
|
return true;
|
|
else if (left->NumSuccsLeft == right->NumSuccsLeft)
|
|
if (left->CycleBound > right->CycleBound)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
|
|
/// Smaller number is the higher priority.
|
|
template<class SF>
|
|
unsigned TDRegReductionPriorityQueue<SF>::
|
|
CalcNodeSethiUllmanNumber(const SUnit *SU) {
|
|
unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
|
|
if (SethiUllmanNumber != 0)
|
|
return SethiUllmanNumber;
|
|
|
|
unsigned Opc = SU->Node->getOpcode();
|
|
if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
|
|
SethiUllmanNumber = 0xffff;
|
|
else if (SU->NumSuccsLeft == 0)
|
|
// If SU does not have a use, i.e. it doesn't produce a value that would
|
|
// be consumed (e.g. store), then it terminates a chain of computation.
|
|
// Give it a small SethiUllman number so it will be scheduled right before
|
|
// its predecessors that it doesn't lengthen their live ranges.
|
|
SethiUllmanNumber = 0;
|
|
else if (SU->NumPredsLeft == 0 &&
|
|
(Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
|
|
SethiUllmanNumber = 0xffff;
|
|
else {
|
|
int Extra = 0;
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue; // ignore chain preds
|
|
SUnit *PredSU = I->first;
|
|
unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
|
|
if (PredSethiUllman > SethiUllmanNumber) {
|
|
SethiUllmanNumber = PredSethiUllman;
|
|
Extra = 0;
|
|
} else if (PredSethiUllman == SethiUllmanNumber && !I->second)
|
|
Extra++;
|
|
}
|
|
|
|
SethiUllmanNumber += Extra;
|
|
}
|
|
|
|
return SethiUllmanNumber;
|
|
}
|
|
|
|
/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
|
|
/// scheduling units.
|
|
template<class SF>
|
|
void TDRegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
|
|
SethiUllmanNumbers.assign(SUnits->size(), 0);
|
|
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
|
|
CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Public Constructor Functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
|
|
SelectionDAG *DAG,
|
|
MachineBasicBlock *BB) {
|
|
const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
|
|
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
|
|
new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII));
|
|
}
|
|
|
|
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
|
|
SelectionDAG *DAG,
|
|
MachineBasicBlock *BB) {
|
|
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
|
|
new TDRegReductionPriorityQueue<td_ls_rr_sort>());
|
|
}
|
|
|