llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-23 05:29:23 +00:00

History

Johnny Chen c6e704df8d Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not

follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99655 91177308-0d34-0410-b5e6-96231b3b80d8

2010-03-26 21:26:28 +00:00

Analysis

rename pred_const_iterator to const_pred_iterator for consistency's sake

2010-03-25 23:25:28 +00:00

Archive

…

AsmParser

Introduce isOpaqueTy and use it rather than isa<OpaqueType>. Also, move some

2010-02-16 14:50:09 +00:00

Bitcode

Finally land the InvokeInst operand reordering.

2010-03-24 13:21:49 +00:00