Jim Grosbach 95923d70d9 remove trailing whitespace ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83213 91177308-0d34-0410-b5e6-96231b3b80d8		2009-10-01 20:45:06 +00:00
..
SubtargetFeature.h
Target.td	Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When	2009-10-01 08:21:18 +00:00
TargetAsmParser.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameInfo.h	Use explicit structs instead of std::pair to map callee saved regs to spill slots.	2009-09-27 17:58:47 +00:00
TargetInstrDesc.h	Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When	2009-10-01 08:21:18 +00:00
TargetInstrInfo.h	Introduce the TargetInstrInfo::KILL machine instruction and get rid of the	2009-09-28 20:32:26 +00:00
TargetInstrItineraries.h	Make the end-of-itinerary mark explicit. Some cleanup.	2009-09-24 20:22:50 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Update comments.	2009-09-19 10:08:51 +00:00
TargetLoweringObjectFile.h	Use OutStreamer.SwitchSection instead of writing out textual section directives.	2009-09-30 22:25:37 +00:00
TargetMachine.h	Add a target hook to add pre- post-regalloc scheduling passes.	2009-09-30 08:49:50 +00:00
TargetMachOWriterInfo.h
TargetOptions.h	Implement the JIT side of the GDB JIT debugging interface. To enable this	2009-09-20 23:52:43 +00:00
TargetRegisterInfo.h	remove trailing whitespace	2009-10-01 20:45:06 +00:00
TargetRegistry.h	remove a dead method.	2009-09-20 22:46:42 +00:00
TargetSchedule.td
TargetSelect.h
TargetSelectionDAG.td
TargetSubtarget.h	Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.	2009-09-30 00:10:16 +00:00