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https://github.com/c64scene-ar/llvm-6502.git
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26a84d4f3c
This is just the framework to identify the needed workarounds. They are not actually implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77902 91177308-0d34-0410-b5e6-96231b3b80d8
202 lines
8.1 KiB
TableGen
202 lines
8.1 KiB
TableGen
//===- Blackfin.td - Describe the Blackfin Target Machine --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Blackfin Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureSDRAM : SubtargetFeature<"sdram", "sdram", "true",
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"Build for SDRAM">;
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def FeatureICPLB : SubtargetFeature<"icplb", "icplb", "true",
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"Assume instruction cache lookaside buffers are enabled at runtime">;
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//===----------------------------------------------------------------------===//
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// Bugs in the silicon becomes workarounds in the compiler.
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// See http://www.analog.com/ for the full list of IC anomalies.
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//===----------------------------------------------------------------------===//
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def WA_MI_SHIFT : SubtargetFeature<"mi-shift-anomaly","wa_mi_shift", "true",
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"Work around 05000074 - "
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"Multi-Issue Instruction with dsp32shiftimm and P-reg Store">;
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def WA_CSYNC : SubtargetFeature<"csync-anomaly","wa_csync", "true",
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"Work around 05000244 - "
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"If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control">;
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def WA_SPECLD : SubtargetFeature<"specld-anomaly","wa_specld", "true",
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"Work around 05000245 - "
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"Access in the Shadow of a Conditional Branch">;
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def WA_HWLOOP : SubtargetFeature<"hwloop-anomaly","wa_hwloop", "true",
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"Work around 05000257 - "
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"Interrupt/Exception During Short Hardware Loop">;
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def WA_MMR_STALL : SubtargetFeature<"mmr-stall-anomaly","wa_mmr_stall", "true",
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"Work around 05000283 - "
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"System MMR Write Is Stalled Indefinitely when Killed">;
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def WA_LCREGS : SubtargetFeature<"lcregs-anomaly","wa_lcregs", "true",
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"Work around 05000312 - "
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"SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted">;
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def WA_KILLED_MMR : SubtargetFeature<"killed-mmr-anomaly",
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"wa_killed_mmr", "true",
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"Work around 05000315 - "
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"Killed System MMR Write Completes Erroneously on Next System MMR Access">;
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def WA_RETS : SubtargetFeature<"rets-anomaly", "wa_rets", "true",
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"Work around 05000371 - "
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"Possible RETS Register Corruption when Subroutine Is under 5 Cycles">;
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def WA_IND_CALL : SubtargetFeature<"ind-call-anomaly", "wa_ind_call", "true",
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"Work around 05000426 - "
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"Speculative Fetches of Indirect-Pointer Instructions">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "BlackfinRegisterInfo.td"
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include "BlackfinCallingConv.td"
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include "BlackfinInstrInfo.td"
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def BlackfinInstrInfo : InstrInfo {}
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//===----------------------------------------------------------------------===//
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// Blackfin processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, string Suffix, list<SubtargetFeature> Features>
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: Processor<!strconcat(Name, Suffix), NoItineraries, Features>;
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def : Proc<"generic", "", []>;
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multiclass Core<string Name,string Suffix,
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list<SubtargetFeature> Features> {
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def : Proc<Name, Suffix, Features>;
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def : Proc<Name, "", Features>;
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def : Proc<Name, "-none", []>;
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}
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multiclass CoreEdinburgh<string Name>
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: Core<Name, "-0.6", [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS]> {
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def : Proc<Name, "-0.5",
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[WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
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WA_RETS]>;
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def : Proc<Name, "-0.4",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS]>;
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def : Proc<Name, "-0.3",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS]>;
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}
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multiclass CoreBraemar<string Name>
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: Core<Name, "-0.3",
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[WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]> {
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def : Proc<Name, "-0.2",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreStirling<string Name>
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: Core<Name, "-0.5", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.4",
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[WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-0.3",
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[WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
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WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
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WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreMoab<string Name>
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: Core<Name, "-0.3", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-0.0",
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[WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreTeton<string Name>
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: Core<Name, "-0.5",
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[WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
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WA_RETS, WA_IND_CALL]> {
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def : Proc<Name, "-0.3",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreKookaburra<string Name>
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: Core<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreMockingbird<string Name>
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: Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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}
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multiclass CoreBrodie<string Name>
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: Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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}
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defm BF512 : CoreBrodie<"bf512">;
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defm BF514 : CoreBrodie<"bf514">;
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defm BF516 : CoreBrodie<"bf516">;
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defm BF518 : CoreBrodie<"bf518">;
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defm BF522 : CoreMockingbird<"bf522">;
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defm BF523 : CoreKookaburra<"bf523">;
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defm BF524 : CoreMockingbird<"bf524">;
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defm BF525 : CoreKookaburra<"bf525">;
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defm BF526 : CoreMockingbird<"bf526">;
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defm BF527 : CoreKookaburra<"bf527">;
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defm BF531 : CoreEdinburgh<"bf531">;
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defm BF532 : CoreEdinburgh<"bf532">;
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defm BF533 : CoreEdinburgh<"bf533">;
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defm BF534 : CoreBraemar<"bf534">;
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defm BF536 : CoreBraemar<"bf536">;
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defm BF537 : CoreBraemar<"bf537">;
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defm BF538 : CoreStirling<"bf538">;
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defm BF539 : CoreStirling<"bf539">;
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defm BF542 : CoreMoab<"bf542">;
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defm BF544 : CoreMoab<"bf544">;
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defm BF548 : CoreMoab<"bf548">;
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defm BF549 : CoreMoab<"bf549">;
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defm BF561 : CoreTeton<"bf561">;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def Blackfin : Target {
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// Pull in Instruction Info:
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let InstructionSet = BlackfinInstrInfo;
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}
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