Richard Osborne c6ff29713d [XCore] The RRegs register class is a superset of GRRegs. ... At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8		2013-04-04 19:57:46 +00:00
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AArch64	AArch64: implement ETMv4 trace system registers.	2013-04-03 12:31:29 +00:00
ARM	Fix pr13145 - Naming a function like a register name confuses the asm parser.	2013-03-19 23:44:03 +00:00
AsmParser	AsmParser: More generic support for integer type suffices.	2013-02-26 20:17:10 +00:00
COFF	[MC][COFF] Delay handling symbol aliases when writing	2013-01-29 22:10:07 +00:00
Disassembler	[XCore] The RRegs register class is a superset of GRRegs.	2013-04-04 19:57:46 +00:00
ELF	Implements low-level object file format specific output for COFF and	2013-04-03 18:31:38 +00:00
MachO	Revert r15266. This fixes llvm.org/pr15266.	2013-02-14 16:23:08 +00:00
Markup	MC: Simple example parser for MC assembly markup.	2012-10-31 23:24:13 +00:00
MBlaze
Mips	Implement the "mips endian" for r_info.	2013-04-03 21:02:51 +00:00
PowerPC	PowerPC: EH adjustments	2013-01-09 17:08:15 +00:00
X86	Add support of RDSEED defined in AVX2 extension	2013-03-28 23:41:26 +00:00