mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
a347f85dbe
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
3.8 KiB
C++
122 lines
3.8 KiB
C++
//===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements the RegisterClassInfo class which provides dynamic
|
|
// information about target register classes. Callee saved and reserved
|
|
// registers depends on calling conventions and other dynamic information, so
|
|
// some things cannot be determined statically.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
|
|
#define LLVM_CODEGEN_REGISTERCLASSINFO_H
|
|
|
|
#include "llvm/ADT/ArrayRef.h"
|
|
#include "llvm/ADT/BitVector.h"
|
|
#include "llvm/ADT/OwningPtr.h"
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
|
|
|
namespace llvm {
|
|
|
|
class RegisterClassInfo {
|
|
struct RCInfo {
|
|
unsigned Tag;
|
|
unsigned NumRegs;
|
|
OwningArrayPtr<unsigned> Order;
|
|
|
|
RCInfo() : Tag(0), NumRegs(0) {}
|
|
operator ArrayRef<unsigned>() const {
|
|
return ArrayRef<unsigned>(Order.get(), NumRegs);
|
|
}
|
|
};
|
|
|
|
// Brief cached information for each register class.
|
|
OwningArrayPtr<RCInfo> RegClass;
|
|
|
|
// Tag changes whenever cached information needs to be recomputed. An RCInfo
|
|
// entry is valid when its tag matches.
|
|
unsigned Tag;
|
|
|
|
const MachineFunction *MF;
|
|
const TargetRegisterInfo *TRI;
|
|
|
|
// Callee saved registers of last MF. Assumed to be valid until the next
|
|
// runOnFunction() call.
|
|
const unsigned *CalleeSaved;
|
|
|
|
// Map register number to CalleeSaved index + 1;
|
|
SmallVector<uint8_t, 4> CSRNum;
|
|
|
|
// Reserved registers in the current MF.
|
|
BitVector Reserved;
|
|
|
|
// Compute all information about RC.
|
|
void compute(const TargetRegisterClass *RC) const;
|
|
|
|
// Return an up-to-date RCInfo for RC.
|
|
const RCInfo &get(const TargetRegisterClass *RC) const {
|
|
const RCInfo &RCI = RegClass[RC->getID()];
|
|
if (Tag != RCI.Tag)
|
|
compute(RC);
|
|
return RCI;
|
|
}
|
|
|
|
public:
|
|
RegisterClassInfo();
|
|
|
|
/// runOnFunction - Prepare to answer questions about MF. This must be called
|
|
/// before any other methods are used.
|
|
void runOnMachineFunction(const MachineFunction &MF);
|
|
|
|
/// getNumAllocatableRegs - Returns the number of actually allocatable
|
|
/// registers in RC in the current function.
|
|
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
|
|
return get(RC).NumRegs;
|
|
}
|
|
|
|
/// getOrder - Returns the preferred allocation order for RC. The order
|
|
/// contains no reserved registers, and registers that alias callee saved
|
|
/// registers come last.
|
|
ArrayRef<unsigned> getOrder(const TargetRegisterClass *RC) const {
|
|
return get(RC);
|
|
}
|
|
|
|
/// getLastCalleeSavedAlias - Returns the last callee saved register that
|
|
/// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
|
|
unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
|
|
assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
|
|
if (unsigned N = CSRNum[PhysReg])
|
|
return CalleeSaved[N-1];
|
|
return 0;
|
|
}
|
|
|
|
/// isReserved - Returns true when PhysReg is a reserved register.
|
|
///
|
|
/// Reserved registers may belong to an allocatable register class, but the
|
|
/// target has explicitly requested that they are not used.
|
|
///
|
|
bool isReserved(unsigned PhysReg) const {
|
|
return Reserved.test(PhysReg);
|
|
}
|
|
|
|
/// isAllocatable - Returns true when PhysReg belongs to an allocatable
|
|
/// register class and it hasn't been reserved.
|
|
///
|
|
/// Allocatable registers may show up in the allocation order of some virtual
|
|
/// register, so a register allocator needs to track its liveness and
|
|
/// availability.
|
|
bool isAllocatable(unsigned PhysReg) const {
|
|
return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
|
|
}
|
|
};
|
|
} // end namespace llvm
|
|
|
|
#endif
|
|
|