Tim Northover e43c5023fe ARM: teach AAPCS-VFP to deal with Cortex-M4. ... Cortex-M4 only has single-precision floating point support, so any LLVM "double" type will have been split into 2 i32s by now. Fortunately, the consecutive-register framework turns out to be precisely what's needed to reconstruct the double and follow AAPCS-VFP correctly! rdar://problem/17012966 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209650 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-27 10:43:38 +00:00
..
Analysis	Adding testcase for PR18886.	2014-05-27 06:44:25 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	ARM: teach AAPCS-VFP to deal with Cortex-M4.	2014-05-27 10:43:38 +00:00
DebugInfo	DebugInfo: Test linkonce-odr functions under LTO.	2014-05-26 06:44:52 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation	[asan] properly instrument memory accesses that have small alignment (smaller than min(8,size)) by making two checks instead of one. This may slowdown some cases, e.g. long long on 32-bit or wide loads produced after loop unrolling. The benefit is higher sencitivity.	2014-05-23 11:52:07 +00:00
Integer
JitListener
Linker	DebugInfo: Generalize some tests to handle variations in attribute ordering.	2014-05-23 21:11:46 +00:00
LTO
MC	AArch64/ARM64: move ARM64 into AArch64's place	2014-05-24 12:50:23 +00:00
Object	llvm/test/Object/ar-error.test: Don't check the message "No such file or directory".	2014-05-24 08:47:11 +00:00
Other
TableGen
tools
Transforms	Convert some X86 blendv* intrinsics into IR.	2014-05-27 03:42:20 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh