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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97891 91177308-0d34-0410-b5e6-96231b3b80d8
340 lines
12 KiB
C++
340 lines
12 KiB
C++
//===-- MBlazeISelDAGToDAG.cpp - A dag to dag inst selector for MBlaze ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MBlaze target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mblaze-isel"
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#include "MBlaze.h"
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#include "MBlazeISelLowering.h"
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#include "MBlazeMachineFunction.h"
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#include "MBlazeRegisterInfo.h"
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#include "MBlazeSubtarget.h"
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#include "MBlazeTargetMachine.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MBlazeDAGToDAGISel - MBlaze specific code to select MBlaze machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace {
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class MBlazeDAGToDAGISel : public SelectionDAGISel {
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/// TM - Keep a reference to MBlazeTargetMachine.
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MBlazeTargetMachine &TM;
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/// Subtarget - Keep a pointer to the MBlazeSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const MBlazeSubtarget &Subtarget;
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public:
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explicit MBlazeDAGToDAGISel(MBlazeTargetMachine &tm) :
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SelectionDAGISel(tm),
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TM(tm), Subtarget(tm.getSubtarget<MBlazeSubtarget>()) {}
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// Pass Name
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virtual const char *getPassName() const {
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return "MBlaze DAG->DAG Pattern Instruction Selection";
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}
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private:
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// Include the pieces autogenerated from the target description.
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#include "MBlazeGenDAGISel.inc"
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/// getTargetMachine - Return a reference to the TargetMachine, casted
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/// to the target-specific type.
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const MBlazeTargetMachine &getTargetMachine() {
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return static_cast<const MBlazeTargetMachine &>(TM);
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}
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/// getInstrInfo - Return a reference to the TargetInstrInfo, casted
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/// to the target-specific type.
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const MBlazeInstrInfo *getInstrInfo() {
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return getTargetMachine().getInstrInfo();
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}
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SDNode *getGlobalBaseReg();
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SDNode *Select(SDNode *N);
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// Complex Pattern.
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bool SelectAddr(SDNode *Op, SDValue N,
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SDValue &Base, SDValue &Offset);
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// Address Selection
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bool SelectAddrRegReg(SDNode *Op, SDValue N, SDValue &Base, SDValue &Index);
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bool SelectAddrRegImm(SDNode *Op, SDValue N, SDValue &Disp, SDValue &Base);
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// getI32Imm - Return a target constant with the specified value, of type i32.
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inline SDValue getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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};
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}
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/// isIntS32Immediate - This method tests to see if the node is either a 32-bit
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/// or 64-bit immediate, and if the value can be accurately represented as a
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/// sign extension from a 32-bit value. If so, this returns true and the
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/// immediate.
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static bool isIntS32Immediate(SDNode *N, int32_t &Imm) {
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unsigned Opc = N->getOpcode();
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if (Opc != ISD::Constant)
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return false;
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Imm = (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
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if (N->getValueType(0) == MVT::i32)
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return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
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else
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return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
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}
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static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
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return isIntS32Immediate(Op.getNode(), Imm);
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}
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/// SelectAddressRegReg - Given the specified addressed, check to see if it
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/// can be represented as an indexed [r+r] operation. Returns false if it
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/// can be more efficiently represented with [r+imm].
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bool MBlazeDAGToDAGISel::
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SelectAddrRegReg(SDNode *Op, SDValue N, SDValue &Base, SDValue &Index) {
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if (N.getOpcode() == ISD::FrameIndex) return false;
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if (N.getOpcode() == ISD::TargetExternalSymbol ||
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N.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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int32_t imm = 0;
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if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
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if (isIntS32Immediate(N.getOperand(1), imm))
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return false; // r+i
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if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable ||
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N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
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return false; // jump tables.
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Base = N.getOperand(1);
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Index = N.getOperand(0);
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return true;
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}
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return false;
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}
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/// Returns true if the address N can be represented by a base register plus
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/// a signed 32-bit displacement [r+imm], and if it is not better
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/// represented as reg+reg.
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bool MBlazeDAGToDAGISel::
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SelectAddrRegImm(SDNode *Op, SDValue N, SDValue &Disp, SDValue &Base) {
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// If this can be more profitably realized as r+r, fail.
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if (SelectAddrRegReg(Op, N, Disp, Base))
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return false;
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if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
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int32_t imm = 0;
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if (isIntS32Immediate(N.getOperand(1), imm)) {
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Disp = CurDAG->getTargetConstant(imm, MVT::i32);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
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} else {
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Base = N.getOperand(0);
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}
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DEBUG( errs() << "WESLEY: Using Operand Immediate\n" );
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return true; // [r+i]
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}
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} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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// Loading from a constant address.
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uint32_t Imm = CN->getZExtValue();
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Disp = CurDAG->getTargetConstant(Imm, CN->getValueType(0));
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Base = CurDAG->getRegister(MBlaze::R0, CN->getValueType(0));
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DEBUG( errs() << "WESLEY: Using Constant Node\n" );
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return true;
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}
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Disp = CurDAG->getTargetConstant(0, TM.getTargetLowering()->getPointerTy());
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
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else
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Base = N;
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return true; // [r+0]
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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SDNode *MBlazeDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
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return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
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}
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/// ComplexPattern used on MBlazeInstrInfo
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/// Used on MBlaze Load/Store instructions
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bool MBlazeDAGToDAGISel::
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SelectAddr(SDNode *Op, SDValue Addr, SDValue &Offset, SDValue &Base) {
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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// on PIC code Load GA
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if (TM.getRelocationModel() == Reloc::PIC_) {
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if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
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(Addr.getOpcode() == ISD::TargetConstantPool) ||
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(Addr.getOpcode() == ISD::TargetJumpTable)){
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Base = CurDAG->getRegister(MBlaze::R15, MVT::i32);
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Offset = Addr;
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return true;
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}
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} else {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_immSExt16(CN)) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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} else {
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Base = Addr.getOperand(0);
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}
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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return true;
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}
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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/// Select instructions not customized! Used for
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/// expanded, promoted and normal instructions
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SDNode* MBlazeDAGToDAGISel::Select(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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DebugLoc dl = Node->getDebugLoc();
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// Dump information about the Node being selected
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DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
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return NULL;
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}
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///
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// Instruction Selection not handled by the auto-generated
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// tablegen selection should be handled here.
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///
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switch(Opcode) {
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default: break;
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// Get target GOT address.
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case ISD::GLOBAL_OFFSET_TABLE:
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return getGlobalBaseReg();
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case ISD::FrameIndex: {
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SDValue imm = CurDAG->getTargetConstant(0, MVT::i32);
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int FI = dyn_cast<FrameIndexSDNode>(Node)->getIndex();
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EVT VT = Node->getValueType(0);
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
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unsigned Opc = MBlaze::ADDI;
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if (Node->hasOneUse())
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return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
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return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
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}
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/// Handle direct and indirect calls when using PIC. On PIC, when
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/// GOT is smaller than about 64k (small code) the GA target is
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/// loaded with only one instruction. Otherwise GA's target must
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/// be loaded with 3 instructions.
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case MBlazeISD::JmpLink: {
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if (TM.getRelocationModel() == Reloc::PIC_) {
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SDValue Chain = Node->getOperand(0);
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SDValue Callee = Node->getOperand(1);
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SDValue R20Reg = CurDAG->getRegister(MBlaze::R20, MVT::i32);
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SDValue InFlag(0, 0);
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if ( (isa<GlobalAddressSDNode>(Callee)) ||
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(isa<ExternalSymbolSDNode>(Callee)) )
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{
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/// Direct call for global addresses and external symbols
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SDValue GPReg = CurDAG->getRegister(MBlaze::R15, MVT::i32);
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// Use load to get GOT target
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SDValue Ops[] = { Callee, GPReg, Chain };
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SDValue Load = SDValue(CurDAG->getMachineNode(MBlaze::LW, dl,
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MVT::i32, MVT::Other, Ops, 3), 0);
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Chain = Load.getValue(1);
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// Call target must be on T9
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Chain = CurDAG->getCopyToReg(Chain, dl, R20Reg, Load, InFlag);
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} else
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/// Indirect call
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Chain = CurDAG->getCopyToReg(Chain, dl, R20Reg, Callee, InFlag);
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// Emit Jump and Link Register
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SDNode *ResNode = CurDAG->getMachineNode(MBlaze::BRLID, dl, MVT::Other,
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MVT::Flag, R20Reg, Chain);
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Chain = SDValue(ResNode, 0);
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InFlag = SDValue(ResNode, 1);
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ReplaceUses(SDValue(Node, 0), Chain);
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ReplaceUses(SDValue(Node, 1), InFlag);
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return ResNode;
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}
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}
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}
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// Select the default instruction
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SDNode *ResNode = SelectCode(Node);
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DEBUG(errs() << "=> ");
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if (ResNode == NULL || ResNode == Node)
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DEBUG(Node->dump(CurDAG));
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else
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DEBUG(ResNode->dump(CurDAG));
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DEBUG(errs() << "\n");
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return ResNode;
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}
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/// createMBlazeISelDag - This pass converts a legalized DAG into a
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/// MBlaze-specific DAG, ready for instruction scheduling.
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FunctionPass *llvm::createMBlazeISelDag(MBlazeTargetMachine &TM) {
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return new MBlazeDAGToDAGISel(TM);
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}
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