Evan Cheng c7cf10c97e LR is in GPR, not tGPR even in Thumb1 mode. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-24 18:00:18 +00:00
..
Alpha
ARM	LR is in GPR, not tGPR even in Thumb1 mode.	2010-05-24 18:00:18 +00:00
Blackfin
CBackend
CellSPU	Make SPU backend not assert on jump tables.	2010-05-11 11:00:02 +00:00
CPP
Generic	Enable a bunch more -regalloc=fast tests	2010-05-12 00:11:24 +00:00
MBlaze
Mips
MSP430
PIC16
PowerPC	Only use clairvoyance when defining a register, and then only if it has one use.	2010-05-17 04:50:57 +00:00
SPARC
SystemZ	SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and	2010-05-14 22:17:42 +00:00
Thumb	Enable a bunch more -regalloc=fast tests	2010-05-12 00:11:24 +00:00
Thumb2	Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by	2010-05-22 00:23:12 +00:00
X86	This test is darwin only. Make it so(tm).	2010-05-22 00:55:55 +00:00
XCore