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c7e18a10d4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22732 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.2 KiB
Plaintext
37 lines
1.2 KiB
Plaintext
TODO:
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* gpr0 allocation
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* implement do-loop -> bdnz transform
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* implement powerpc-64 for darwin
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* use stfiwx in float->int
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* be able to combine sequences like the following into 2 instructions:
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lis r2, ha16(l2__ZTV4Cell)
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la r2, lo16(l2__ZTV4Cell)(r2)
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addi r2, r2, 8
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* Support 'update' load/store instructions. These are cracked on the G5, but
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are still a codesize win.
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* Add a custom legalizer for the GlobalAddress node, to move the funky darwin
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stub stuff from the instruction selector to the legalizer (exposing low-level
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operations to the dag for optzn. For example, we want to codegen this:
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int A = 0;
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void B() { A++; }
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as:
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lis r9,ha16(_A)
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lwz r2,lo16(_A)(r9)
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addi r2,r2,1
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stw r2,lo16(_A)(r9)
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not:
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lis r2, ha16(_A)
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lwz r2, lo16(_A)(r2)
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addi r2, r2, 1
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lis r3, ha16(_A)
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stw r2, lo16(_A)(r3)
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* should hint to the branch select pass that it doesn't need to print the
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second unconditional branch, so we don't end up with things like:
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b .LBBl42__2E_expand_function_8_674 ; loopentry.24
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b .LBBl42__2E_expand_function_8_42 ; NewDefault
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b .LBBl42__2E_expand_function_8_42 ; NewDefault
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