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c7f3ace20c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
221 lines
8.2 KiB
C++
221 lines
8.2 KiB
C++
//===- MBlazeInstrInfo.cpp - MBlaze Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MBlaze implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MBlazeInstrInfo.h"
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#include "MBlazeTargetMachine.h"
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#include "MBlazeMachineFunction.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "MBlazeGenInstrInfo.inc"
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using namespace llvm;
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MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
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: TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts)),
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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bool MBlazeInstrInfo::
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isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
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SrcSubIdx = DstSubIdx = 0; // No sub-registers.
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// add $dst, $src, $zero || addu $dst, $zero, $src
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// or $dst, $src, $zero || or $dst, $zero, $src
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if ((MI.getOpcode() == MBlaze::ADD) || (MI.getOpcode() == MBlaze::OR)) {
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if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == MBlaze::R0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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return true;
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} else if (MI.getOperand(2).isReg() &&
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MI.getOperand(2).getReg() == MBlaze::R0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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}
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// addi $dst, $src, 0
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// ori $dst, $src, 0
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if ((MI.getOpcode() == MBlaze::ADDI) || (MI.getOpcode() == MBlaze::ORI)) {
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if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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}
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MBlazeInstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {
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if (MI->getOpcode() == MBlaze::LWI) {
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if ((MI->getOperand(2).isFI()) && // is a stack slot
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(MI->getOperand(1).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(1)))) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MBlazeInstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
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if (MI->getOpcode() == MBlaze::SWI) {
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if ((MI->getOperand(2).isFI()) && // is a stack slot
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(MI->getOperand(1).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(1)))) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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void MBlazeInstrInfo::
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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BuildMI(MBB, MI, DL, get(MBlaze::NOP));
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}
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bool MBlazeInstrInfo::
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copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL;
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llvm::BuildMI(MBB, I, DL, get(MBlaze::ADD), DestReg)
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.addReg(SrcReg).addReg(MBlaze::R0);
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return true;
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}
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void MBlazeInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL;
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BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
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.addImm(0).addFrameIndex(FI);
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}
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void MBlazeInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL;
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BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
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.addImm(0).addFrameIndex(FI);
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}
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MachineInstr *MBlazeInstrInfo::
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foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops, int FI) const {
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if (Ops.size() != 1) return NULL;
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MachineInstr *NewMI = NULL;
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switch (MI->getOpcode()) {
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case MBlaze::OR:
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case MBlaze::ADD:
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if ((MI->getOperand(0).isReg()) &&
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(MI->getOperand(2).isReg()) &&
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(MI->getOperand(2).getReg() == MBlaze::R0) &&
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(MI->getOperand(1).isReg())) {
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if (Ops[0] == 0) { // COPY -> STORE
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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bool isUndef = MI->getOperand(1).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(MBlaze::SW))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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.addImm(0).addFrameIndex(FI);
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} else { // COPY -> LOAD
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unsigned DstReg = MI->getOperand(0).getReg();
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bool isDead = MI->getOperand(0).isDead();
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bool isUndef = MI->getOperand(0).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(MBlaze::LW))
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.addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
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getUndefRegState(isUndef))
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.addImm(0).addFrameIndex(FI);
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}
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}
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break;
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}
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return NewMI;
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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unsigned MBlazeInstrInfo::
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InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// Can only insert uncond branches so far.
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assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
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BuildMI(&MBB, DebugLoc(), get(MBlaze::BRI)).addMBB(TBB);
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return 1;
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}
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/// getGlobalBaseReg - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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/// initialize the register in the function entry block, if necessary.
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///
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unsigned MBlazeInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
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MBlazeFunctionInfo *MBlazeFI = MF->getInfo<MBlazeFunctionInfo>();
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unsigned GlobalBaseReg = MBlazeFI->getGlobalBaseReg();
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if (GlobalBaseReg != 0)
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return GlobalBaseReg;
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = MF->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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GlobalBaseReg = RegInfo.createVirtualRegister(MBlaze::CPURegsRegisterClass);
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bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, MBlaze::R20,
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MBlaze::CPURegsRegisterClass,
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MBlaze::CPURegsRegisterClass);
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assert(Ok && "Couldn't assign to global base register!");
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Ok = Ok; // Silence warning when assertions are turned off.
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RegInfo.addLiveIn(MBlaze::R20);
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MBlazeFI->setGlobalBaseReg(GlobalBaseReg);
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return GlobalBaseReg;
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}
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