John Brawn 151a5da534 [ARM] Fix handling of thumb1 out-of-range frame offsets ... LocalStackSlotPass assumes that isFrameOffsetLegal doesn't change its answer when the base register changes. Unfortunately this isn't true in thumb1, where SP-based loads allow a larger offset than non-SP-based loads, and this causes the base register reuse code to generate instructions that are unencodable, causing an assertion failure. Solve this by adding a BaseReg parameter to isFrameOffsetLegal, which ARMBaseRegisterInfo can then make use of to give the correct answer. Differential Revision: http://reviews.llvm.org/D8419 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232825 91177308-0d34-0410-b5e6-96231b3b80d8		2015-03-20 17:20:07 +00:00
..
AArch64
ARM	Fix a nasty bug in DAGCombine of STORE nodes.	2015-03-19 22:48:57 +00:00
BPF
CPP
Generic	Unxfail test/CodeGen/Generic/vector.ll now passing on Hexagon	2015-03-19 20:22:17 +00:00
Hexagon	[Hexagon] Add support for vector instructions	2015-03-19 16:33:08 +00:00
Inputs
Mips
MSP430
NVPTX	Add support for __nvvm_reflect changes in libdevice in CUDA-7.0	2015-03-19 17:05:35 +00:00
PowerPC	Fix a nasty bug in DAGCombine of STORE nodes.	2015-03-19 22:48:57 +00:00
R600	R600/SI: Add missing CHECK-LABEL lines to a test	2015-03-20 03:12:42 +00:00
SPARC
SystemZ
Thumb	[ARM] Fix handling of thumb1 out-of-range frame offsets	2015-03-20 17:20:07 +00:00
Thumb2	Fix a nasty bug in DAGCombine of STORE nodes.	2015-03-19 22:48:57 +00:00
WinEH	WinEH: Make llvm.eh.actions emission match the EH docs	2015-03-19 22:31:02 +00:00
X86	[MBP] Don't outline short optional branches	2015-03-20 10:00:37 +00:00
XCore