mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 00:11:00 +00:00
49cab03c81
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6340 91177308-0d34-0410-b5e6-96231b3b80d8
460 lines
15 KiB
C++
460 lines
15 KiB
C++
//===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
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//
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// This file contains a printer that converts from our internal representation
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// of LLVM code to a nice human readable form that is suitable for debuggging.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/Constant.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "Support/Statistic.h"
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namespace {
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struct Printer : public MachineFunctionPass {
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std::ostream &O;
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unsigned ConstIdx;
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Printer(std::ostream &o) : O(o), ConstIdx(0) {}
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virtual const char *getPassName() const {
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return "X86 Assembly Printer";
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}
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void printConstantPool(MachineConstantPool *MCP, const TargetData &TD);
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bool runOnMachineFunction(MachineFunction &F);
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};
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}
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/// createX86CodePrinterPass - Print out the specified machine code function to
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/// the specified stream. This function should work regardless of whether or
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/// not the function is in SSA form or not.
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///
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Pass *createX86CodePrinterPass(std::ostream &O) {
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return new Printer(O);
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}
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// printConstantPool - Print out any constants which have been spilled to
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// memory...
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void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){
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const std::vector<Constant*> &CP = MCP->getConstants();
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if (CP.empty()) return;
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for (unsigned i = 0, e = CP.size(); i != e; ++i) {
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O << "\t.section .rodata\n";
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O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n";
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O << ".CPI" << i+ConstIdx << ":\t\t\t\t\t;" << *CP[i] << "\n";
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O << "\t*Constant output not implemented yet!*\n\n";
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}
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ConstIdx += CP.size(); // Don't recycle constant pool index numbers
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}
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/// runOnFunction - This uses the X86InstructionInfo::print method
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/// to print assembly for each instruction.
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bool Printer::runOnMachineFunction(MachineFunction &MF) {
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static unsigned BBNumber = 0;
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const TargetMachine &TM = MF.getTarget();
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const TargetInstrInfo &TII = TM.getInstrInfo();
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// Print out constants referenced by the function
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printConstantPool(MF.getConstantPool(), TM.getTargetData());
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// Print out labels for the function.
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O << "\t.text\n";
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O << "\t.align 16\n";
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O << "\t.globl\t" << MF.getFunction()->getName() << "\n";
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O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n";
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O << MF.getFunction()->getName() << ":\n";
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// Print out code for the function.
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block.
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O << ".BB" << BBNumber++ << ":\n";
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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O << "\t";
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TII.print(*II, O, TM);
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}
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}
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// We didn't modify anything.
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return false;
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}
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static bool isScale(const MachineOperand &MO) {
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return MO.isImmediate() &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
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}
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static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFrameIndex()) return true;
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if (MI->getOperand(Op).isConstantPoolIndex()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
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}
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static void printOp(std::ostream &O, const MachineOperand &MO,
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const MRegisterInfo &RI) {
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (Value *V = MO.getVRegValueOrNull()) {
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O << "<" << V->getName() << ">";
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return;
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp:
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O << "<" << MO.getVRegValue()->getName() << ">";
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return;
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case MachineOperand::MO_GlobalAddress:
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O << "<" << MO.getGlobal()->getName() << ">";
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return;
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case MachineOperand::MO_ExternalSymbol:
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O << "<" << MO.getSymbolName() << ">";
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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}
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static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
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switch (Desc.TSFlags & X86II::ArgMask) {
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default: assert(0 && "Unknown arg size!");
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case X86II::Arg8: return "BYTE PTR";
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case X86II::Arg16: return "WORD PTR";
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case X86II::Arg32: return "DWORD PTR";
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case X86II::Arg64: return "QWORD PTR";
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case X86II::ArgF32: return "DWORD PTR";
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case X86II::ArgF64: return "QWORD PTR";
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case X86II::ArgF80: return "XWORD PTR";
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}
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}
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static void printMemReference(std::ostream &O, const MachineInstr *MI,
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unsigned Op, const MRegisterInfo &RI) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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if (MI->getOperand(Op).isFrameIndex()) {
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O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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} else if (MI->getOperand(Op).isConstantPoolIndex()) {
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O << "[.CPI" << MI->getOperand(Op).getConstantPoolIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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}
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const MachineOperand &BaseReg = MI->getOperand(Op);
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int ScaleVal = MI->getOperand(Op+1).getImmedValue();
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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int DispVal = MI->getOperand(Op+3).getImmedValue();
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O << "[";
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bool NeedPlus = false;
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if (BaseReg.getReg()) {
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printOp(O, BaseReg, RI);
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NeedPlus = true;
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}
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if (IndexReg.getReg()) {
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if (NeedPlus) O << " + ";
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if (ScaleVal != 1)
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O << ScaleVal << "*";
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printOp(O, IndexReg, RI);
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NeedPlus = true;
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}
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if (DispVal) {
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if (NeedPlus)
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if (DispVal > 0)
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O << " + ";
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else {
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O << " - ";
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DispVal = -DispVal;
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}
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O << DispVal;
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}
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O << "]";
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}
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// print - Print out an x86 instruction in intel syntax
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void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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const TargetMachine &TM) const {
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unsigned Opcode = MI->getOpcode();
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const TargetInstrDescriptor &Desc = get(Opcode);
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::Pseudo:
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if (Opcode == X86::PHI) {
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printOp(O, MI->getOperand(0), RI);
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O << " = phi ";
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
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if (i != 1) O << ", ";
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O << "[";
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printOp(O, MI->getOperand(i), RI);
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O << ", ";
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printOp(O, MI->getOperand(i+1), RI);
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O << "]";
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}
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} else {
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unsigned i = 0;
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if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() ||
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MI->getOperand(0).opIsDefAndUse())) {
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printOp(O, MI->getOperand(0), RI);
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O << " = ";
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++i;
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}
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O << getName(MI->getOpcode());
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for (unsigned e = MI->getNumOperands(); i != e; ++i) {
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O << " ";
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if (MI->getOperand(i).opIsDefOnly() ||
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MI->getOperand(i).opIsDefAndUse()) O << "*";
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printOp(O, MI->getOperand(i), RI);
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if (MI->getOperand(i).opIsDefOnly() ||
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MI->getOperand(i).opIsDefAndUse()) O << "*";
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}
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}
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O << "\n";
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return;
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case X86II::RawFrm:
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// The accepted forms of Raw instructions are:
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// 1. nop - No operand required
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// 2. jmp foo - PC relative displacement operand
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// 3. call bar - GlobalAddress Operand or External Symbol Operand
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//
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assert(MI->getNumOperands() == 0 ||
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(MI->getNumOperands() == 1 &&
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(MI->getOperand(0).isPCRelativeDisp() ||
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MI->getOperand(0).isGlobalAddress() ||
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MI->getOperand(0).isExternalSymbol())) &&
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"Illegal raw instruction!");
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O << getName(MI->getOpcode()) << " ";
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if (MI->getNumOperands() == 1) {
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printOp(O, MI->getOperand(0), RI);
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}
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O << "\n";
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return;
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case X86II::AddRegFrm: {
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// There are currently two forms of acceptable AddRegFrm instructions.
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// Either the instruction JUST takes a single register (like inc, dec, etc),
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// or it takes a register and an immediate of the same size as the register
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// (move immediate f.e.). Note that this immediate value might be stored as
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// an LLVM value, to represent, for example, loading the address of a global
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// into a register. The initial register might be duplicated if this is a
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// M_2_ADDR_REG instruction
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//
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 1 ||
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(MI->getNumOperands() == 2 &&
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(MI->getOperand(1).getVRegValueOrNull() ||
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MI->getOperand(1).isImmediate() ||
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MI->getOperand(1).isRegister() ||
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MI->getOperand(1).isGlobalAddress() ||
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MI->getOperand(1).isExternalSymbol()))) &&
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"Illegal form for AddRegFrm instruction!");
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unsigned Reg = MI->getOperand(0).getReg();
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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if (MI->getNumOperands() == 2 &&
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(!MI->getOperand(1).isRegister() ||
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MI->getOperand(1).getVRegValueOrNull() ||
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MI->getOperand(1).isGlobalAddress() ||
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MI->getOperand(1).isExternalSymbol())) {
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O << ", ";
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printOp(O, MI->getOperand(1), RI);
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}
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O << "\n";
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return;
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}
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case X86II::MRMDestReg: {
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// There are two acceptable forms of MRMDestReg instructions, those with 2,
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// 3 and 4 operands:
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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// 3 Operands: in this form, the first two registers (the destination, and
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// the first operand) should be the same, post register allocation. The 3rd
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// operand is an additional input. This should be for things like add
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// instructions.
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//
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// 4 Operands: This form is for instructions which are 3 operands forms, but
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// have a constant argument as well.
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//
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bool isTwoAddr = isTwoAddrInstr(Opcode);
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(isTwoAddr && MI->getOperand(1).isRegister() &&
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MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
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(MI->getNumOperands() == 3 ||
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(MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate()))))
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&& "Bad format for MRMDestReg!");
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(1+isTwoAddr), RI);
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if (MI->getNumOperands() == 4) {
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O << ", ";
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printOp(O, MI->getOperand(3), RI);
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}
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O << "\n";
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return;
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}
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case X86II::MRMDestMem: {
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// These instructions are the same as MRMDestReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
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MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
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O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
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printMemReference(O, MI, 0, RI);
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O << ", ";
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printOp(O, MI->getOperand(4), RI);
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O << "\n";
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return;
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}
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case X86II::MRMSrcReg: {
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// There is a two forms that are acceptable for MRMSrcReg instructions,
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// those with 3 and 2 operands:
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//
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// 3 Operands: in this form, the last register (the second input) is the
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// ModR/M input. The first two operands should be the same, post register
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// allocation. This is for things like: add r32, r/m32
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(MI->getOperand(0).isRegister() &&
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MI->getOperand(1).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
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&& "Bad format for MRMSrcReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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O << "\n";
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return;
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}
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case X86II::MRMSrcMem: {
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// These instructions are the same as MRMSrcReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
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(MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
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isMem(MI, 2))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 2+4 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", " << sizePtr(Desc) << " ";
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printMemReference(O, MI, MI->getNumOperands()-4, RI);
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O << "\n";
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return;
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}
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case X86II::MRMS0r: case X86II::MRMS1r:
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case X86II::MRMS2r: case X86II::MRMS3r:
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case X86II::MRMS4r: case X86II::MRMS5r:
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case X86II::MRMS6r: case X86II::MRMS7r: {
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// In this form, the following are valid formats:
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// 1. sete r
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// 2. cmp reg, immediate
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// 2. shl rdest, rinput <implicit CL or 1>
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// 3. sbb rdest, rinput, immediate [rdest = rinput]
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//
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assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
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MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
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assert((MI->getNumOperands() != 2 ||
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MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
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"Bad MRMSxR format!");
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assert((MI->getNumOperands() < 3 ||
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(MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
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"Bad MRMSxR format!");
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if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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}
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O << "\n";
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return;
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}
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case X86II::MRMS0m: case X86II::MRMS1m:
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case X86II::MRMS2m: case X86II::MRMS3m:
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case X86II::MRMS4m: case X86II::MRMS5m:
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case X86II::MRMS6m: case X86II::MRMS7m: {
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// In this form, the following are valid formats:
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// 1. sete [m]
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// 2. cmp [m], immediate
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// 2. shl [m], rinput <implicit CL or 1>
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// 3. sbb [m], immediate
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//
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assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
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isMem(MI, 0) && "Bad MRMSxM format!");
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assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) &&
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"Bad MRMSxM format!");
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O << getName(MI->getOpCode()) << " ";
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O << sizePtr(Desc) << " ";
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printMemReference(O, MI, 0, RI);
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if (MI->getNumOperands() == 5) {
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O << ", ";
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printOp(O, MI->getOperand(4), RI);
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}
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O << "\n";
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return;
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}
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default:
|
|
O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;
|
|
}
|
|
}
|