mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-14 13:07:31 +00:00
7d24705f65
callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
131 lines
5.7 KiB
LLVM
131 lines
5.7 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
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%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
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%struct.__neon_int64x1x4_t = type { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }
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%struct.__neon_int8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
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%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
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define <8 x i8> @vld4i8(i8* %A) nounwind {
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;CHECK: vld4i8:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64]
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%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
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%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
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%tmp4 = add <8 x i8> %tmp2, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vld4i16(i16* %A) nounwind {
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;CHECK: vld4i16:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 16)
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%tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2
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%tmp4 = add <4 x i16> %tmp2, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vld4i32(i32* %A) nounwind {
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;CHECK: vld4i32:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 32)
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%tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2
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%tmp4 = add <2 x i32> %tmp2, %tmp3
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ret <2 x i32> %tmp4
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}
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define <2 x float> @vld4f(float* %A) nounwind {
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;CHECK: vld4f:
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;CHECK: vld4.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 2
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%tmp4 = fadd <2 x float> %tmp2, %tmp3
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ret <2 x float> %tmp4
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}
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define <1 x i64> @vld4i64(i64* %A) nounwind {
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;CHECK: vld4i64:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld1.64 {d16, d17, d18, d19}, [r0, :256]
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64)
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%tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
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%tmp4 = add <1 x i64> %tmp2, %tmp3
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ret <1 x i64> %tmp4
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}
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define <16 x i8> @vld4Qi8(i8* %A) nounwind {
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;CHECK: vld4Qi8:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]!
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;CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]
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%tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 64)
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%tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
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%tmp4 = add <16 x i8> %tmp2, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vld4Qi16(i16* %A) nounwind {
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;CHECK: vld4Qi16:
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;Check for no alignment specifier.
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;CHECK: vld4.16 {d16, d18, d20, d22}, [r0]!
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;CHECK: vld4.16 {d17, d19, d21, d23}, [r0]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
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%tmp4 = add <8 x i16> %tmp2, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vld4Qi32(i32* %A) nounwind {
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;CHECK: vld4Qi32:
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;CHECK: vld4.32
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;CHECK: vld4.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2
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%tmp4 = add <4 x i32> %tmp2, %tmp3
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ret <4 x i32> %tmp4
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}
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define <4 x float> @vld4Qf(float* %A) nounwind {
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;CHECK: vld4Qf:
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;CHECK: vld4.32
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;CHECK: vld4.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2
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%tmp4 = fadd <4 x float> %tmp2, %tmp3
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ret <4 x float> %tmp4
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}
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declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8*, i32) nounwind readonly
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declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*, i32) nounwind readonly
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declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8*, i32) nounwind readonly
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declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8*, i32) nounwind readonly
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declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8*, i32) nounwind readonly
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declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8*, i32) nounwind readonly
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declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8*, i32) nounwind readonly
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