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https://github.com/c64scene-ar/llvm-6502.git
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c8bfd1d78f
flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
1.4 KiB
LLVM
72 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
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define float @t1(float %acc, float %a, float %b) nounwind {
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entry:
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; VFP2: t1:
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; VFP2: vnmla.f32
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; NEON: t1:
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; NEON: vnmla.f32
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; A8: t1:
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; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}}
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; A8: vsub.f32 d0, d0, d1
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%0 = fmul float %a, %b
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%1 = fsub float -0.0, %0
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%2 = fsub float %1, %acc
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ret float %2
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}
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define float @t2(float %acc, float %a, float %b) nounwind {
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entry:
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; VFP2: t2:
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; VFP2: vnmla.f32
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; NEON: t2:
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; NEON: vnmla.f32
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; A8: t2:
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; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}}
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; A8: vsub.f32 d0, d0, d1
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%0 = fmul float %a, %b
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%1 = fmul float -1.0, %0
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%2 = fsub float %1, %acc
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ret float %2
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}
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define double @t3(double %acc, double %a, double %b) nounwind {
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entry:
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; VFP2: t3:
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; VFP2: vnmla.f64
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; NEON: t3:
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; NEON: vnmla.f64
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; A8: t3:
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; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}}
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; A8: vsub.f64 d16, d16, d17
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%0 = fmul double %a, %b
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%1 = fsub double -0.0, %0
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%2 = fsub double %1, %acc
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ret double %2
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}
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define double @t4(double %acc, double %a, double %b) nounwind {
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entry:
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; VFP2: t4:
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; VFP2: vnmla.f64
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; NEON: t4:
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; NEON: vnmla.f64
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; A8: t4:
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; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}}
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; A8: vsub.f64 d16, d16, d17
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%0 = fmul double %a, %b
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%1 = fmul double -1.0, %0
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%2 = fsub double %1, %acc
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ret double %2
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}
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