Nate Begeman 2ea8ee7c76 Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8		2010-12-10 00:26:57 +00:00
..
Alpha
ARM	ARM stm/ldm instructions require more than one register in the register list.	2010-12-09 18:31:13 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips	Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka	2010-12-09 17:32:30 +00:00
MSP430
PowerPC
PTX
SPARC
SystemZ
Thumb
Thumb2	ARM stm/ldm instructions require more than one register in the register list.	2010-12-09 18:31:13 +00:00
X86	Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.	2010-12-10 00:26:57 +00:00
XCore
thumb2-mul.ll