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The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96969 91177308-0d34-0410-b5e6-96231b3b80d8
247 lines
6.3 KiB
C++
247 lines
6.3 KiB
C++
//===- MBlazeInstrFormats.td - MB Instruction defs --------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Describe MBlaze instructions format
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//
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// CPU INSTRUCTION FORMATS
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//
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// opcode - operation code.
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// rd - dst reg.
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// ra - first src. reg.
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// rb - second src. reg.
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// imm16 - 16-bit immediate value.
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//
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//===----------------------------------------------------------------------===//
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// Generic MBlaze Format
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class MBlazeInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin> : Instruction
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{
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field bits<32> Inst;
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let Namespace = "MBlaze";
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bits<6> opcode;
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// Top 6 bits are the 'opcode' field
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let Inst{0-5} = opcode;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Itinerary = itin;
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instruction class
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//===----------------------------------------------------------------------===//
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class MBlazePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MBlazeInst<outs, ins, asmstr, pattern, IIPseudo>;
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//===----------------------------------------------------------------------===//
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// Type A instruction class in MBlaze : <|opcode|rd|ra|rb|flags|>
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//===----------------------------------------------------------------------===//
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class TA<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> rd;
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bits<5> ra;
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bits<5> rb;
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let opcode = op;
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let Inst{6-10} = rd;
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let Inst{11-15} = ra;
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let Inst{16-20} = rb;
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let Inst{21-31} = flags;
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}
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class TAI<bits<6> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> rd;
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bits<5> ra;
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bits<16> imm16;
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let opcode = op;
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let Inst{6-10} = rd;
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let Inst{11-15} = ra;
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let Inst{16-31} = imm16;
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}
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class TIMM<bits<6> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> ra;
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bits<16> imm16;
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let opcode = op;
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let Inst{6-15} = 0;
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let Inst{16-31} = imm16;
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}
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class TADDR<bits<6> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<26> addr;
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let opcode = op;
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let Inst{6-31} = addr;
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}
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//===----------------------------------------------------------------------===//
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// Type B instruction class in MBlaze : <|opcode|rd|ra|immediate|>
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//===----------------------------------------------------------------------===//
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class TB<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> rd;
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bits<5> ra;
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bits<16> imm16;
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let opcode = op;
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let Inst{6-10} = rd;
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let Inst{11-15} = ra;
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let Inst{16-31} = imm16;
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}
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//===----------------------------------------------------------------------===//
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// Float instruction class in MBlaze : <|opcode|rd|ra|flags|>
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//===----------------------------------------------------------------------===//
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class TF<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> rd;
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bits<5> ra;
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let opcode = op;
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let Inst{6-10} = rd;
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let Inst{11-15} = ra;
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let Inst{16-20} = 0;
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let Inst{21-31} = flags;
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}
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//===----------------------------------------------------------------------===//
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// Branch instruction class in MBlaze : <|opcode|rd|br|ra|flags|>
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//===----------------------------------------------------------------------===//
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class TBR<bits<6> op, bits<5> br, bits<11> flags, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> ra;
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let opcode = op;
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let Inst{6-10} = 0;
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let Inst{11-15} = br;
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let Inst{16-20} = ra;
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let Inst{21-31} = flags;
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}
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class TBRC<bits<6> op, bits<5> br, bits<11> flags, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> ra;
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bits<5> rb;
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let opcode = op;
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let Inst{6-10} = br;
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let Inst{11-15} = ra;
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let Inst{16-20} = rb;
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let Inst{21-31} = flags;
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}
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class TBRL<bits<6> op, bits<5> br, bits<11> flags, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> ra;
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let opcode = op;
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let Inst{6-10} = 0xF;
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let Inst{11-15} = br;
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let Inst{16-20} = ra;
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let Inst{21-31} = flags;
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}
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class TBRI<bits<6> op, bits<5> br, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<16> imm16;
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let opcode = op;
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let Inst{6-10} = 0;
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let Inst{11-15} = br;
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let Inst{16-31} = imm16;
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}
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class TBRLI<bits<6> op, bits<5> br, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<16> imm16;
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let opcode = op;
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let Inst{6-10} = 0xF;
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let Inst{11-15} = br;
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let Inst{16-31} = imm16;
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}
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class TBRCI<bits<6> op, bits<5> br, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> ra;
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bits<16> imm16;
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let opcode = op;
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let Inst{6-10} = br;
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let Inst{11-15} = ra;
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let Inst{16-31} = imm16;
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}
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class TRET<bits<6> op, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<outs, ins, asmstr, pattern, itin>
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{
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bits<5> ra;
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bits<16> imm16;
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let opcode = op;
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let Inst{6-10} = 0x10;
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let Inst{11-15} = ra;
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let Inst{16-31} = imm16;
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}
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