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https://github.com/c64scene-ar/llvm-6502.git
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9a256300f8
Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
650 B
LLVM
18 lines
650 B
LLVM
; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=CONFIG-CHECK %s
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; ELF-CHECK: Format: ELF32
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; ELF-CHECK: Name: .AMDGPU.config
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; CONFIG-CHECK: .section .AMDGPU.config
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; CONFIG-CHECK-NEXT: .long 45096
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; CONFIG-CHECK-NEXT: .long 0
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define void @test(i32 %p) {
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%i = add i32 %p, 2
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%r = bitcast i32 %i to float
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r)
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ret void
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}
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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