Evan Cheng 055b0310f8 Implement Thumb2 ldr. ... After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8		2009-06-29 07:51:04 +00:00
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Alpha
ARM	Implement Thumb2 ldr.	2009-06-29 07:51:04 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU	Add some generic expansion logic for SMULO and UMULO. Fixes UMULO	2009-06-16 06:58:29 +00:00
CPP	Fix code emission for conditional branches.	2009-05-04 19:10:38 +00:00
Generic	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
IA64
Mips	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
MSP430	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
PowerPC	Don't grep the -debug output. This isn't the way to test changes.	2009-06-25 21:59:32 +00:00
SPARC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
Thumb	We should run these tests as well.	2009-06-24 21:36:26 +00:00
Thumb2	Implement Thumb2 ldr.	2009-06-29 07:51:04 +00:00
X86	factor some logic out into a helper function, allow remat of loads from constant	2009-06-27 04:38:55 +00:00
XCore	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00