Bill Wendling a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal ... shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8		2011-03-01 01:00:59 +00:00
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Alpha	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
ARM	Narrow right shifts need to encode their immediates differently from a normal	2011-03-01 01:00:59 +00:00
Blackfin
CBackend
CellSPU	fix visitShift to properly zero extend the shift amount if the provided operand	2011-02-13 09:02:52 +00:00
CPP
Generic	Make this test x86 specific because the ARM backend can't handle it.	2011-02-28 12:30:47 +00:00
MBlaze	fix visitShift to properly zero extend the shift amount if the provided operand	2011-02-13 09:02:52 +00:00
Mips	Disable this test for now...	2011-02-11 02:59:08 +00:00
MSP430	Enhance ComputeMaskedBits to know that aligned frameindexes	2011-02-13 22:25:43 +00:00
PowerPC	Restore the behavior of frame lowering before my refactoring.	2010-12-18 19:53:14 +00:00
PTX	Add preliminary support for .f32 in the PTX backend.	2011-02-28 06:34:09 +00:00
SPARC	Generate correct Sparc32 ABI compliant code for functions that return a struct.	2011-02-21 03:42:44 +00:00
SystemZ	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
Thumb	Sorry, several patches in one.	2011-01-20 08:34:58 +00:00
Thumb2	Move a test that ended up in the wrong place.	2011-02-05 04:15:50 +00:00
X86	Windows codegen also dies on this, so restrict to the platform it was	2011-02-28 14:22:08 +00:00
XCore	Add XCore intrinsic for eeu instruction.	2011-02-24 13:39:18 +00:00