mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-27 15:29:51 +00:00
Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208327 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
1.4 KiB
ArmAsm
39 lines
1.4 KiB
ArmAsm
# Instructions that should be valid but currently fail for known reasons (e.g.
|
|
# they aren't implemented yet).
|
|
# This test is set up to XPASS if any instruction generates an encoding.
|
|
#
|
|
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
|
|
# CHECK-NOT: encoding
|
|
# XFAIL: *
|
|
|
|
.set noat
|
|
c.eq.d $fcc1,$f15,$f15
|
|
c.eq.s $fcc5,$f24,$f17
|
|
c.f.d $fcc4,$f11,$f21
|
|
c.f.s $fcc4,$f30,$f7
|
|
c.le.d $fcc4,$f18,$f1
|
|
c.le.s $fcc6,$f24,$f4
|
|
c.lt.d $fcc3,$f9,$f3
|
|
c.lt.s $fcc2,$f17,$f14
|
|
c.nge.d $fcc5,$f21,$f16
|
|
c.nge.s $fcc3,$f11,$f8
|
|
c.ngl.s $fcc2,$f31,$f23
|
|
c.ngle.s $fcc2,$f18,$f23
|
|
c.ngt.d $fcc4,$f24,$f7
|
|
c.ngt.s $fcc5,$f8,$f13
|
|
c.ole.d $fcc2,$f16,$f31
|
|
c.ole.s $fcc3,$f7,$f20
|
|
c.olt.d $fcc4,$f19,$f28
|
|
c.olt.s $fcc6,$f20,$f7
|
|
c.seq.d $fcc4,$f31,$f7
|
|
c.seq.s $fcc7,$f1,$f25
|
|
c.ueq.d $fcc4,$f13,$f25
|
|
c.ueq.s $fcc6,$f3,$f30
|
|
c.ule.d $fcc7,$f25,$f18
|
|
c.ule.s $fcc7,$f21,$f30
|
|
c.ult.d $fcc6,$f6,$f17
|
|
c.ult.s $fcc7,$f24,$f10
|
|
c.un.d $fcc6,$f23,$f24
|
|
c.un.s $fcc1,$f30,$f4
|
|
rorv $13,$a3,$s5
|