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The advanced copy optimization does not yield any difference on the whole llvm test-suite + SPECs, either in compile time or runtime (binaries are identical), but has a big potential when data go back and forth between register files as demonstrated with test/CodeGen/ARM/adv-copy-opt.ll. Note: This was measured for both Os and O3 for armv7s, arm64, and x86_64. <rdar://problem/12702965> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216236 91177308-0d34-0410-b5e6-96231b3b80d8
1447 lines
55 KiB
C++
1447 lines
55 KiB
C++
//===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Perform peephole optimizations on the machine code:
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//
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// - Optimize Extensions
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//
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// Optimization of sign / zero extension instructions. It may be extended to
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// handle other instructions with similar properties.
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//
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// On some targets, some instructions, e.g. X86 sign / zero extension, may
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// leave the source value in the lower part of the result. This optimization
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// will replace some uses of the pre-extension value with uses of the
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// sub-register of the results.
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//
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// - Optimize Comparisons
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//
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// Optimization of comparison instructions. For instance, in this code:
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//
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// sub r1, 1
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// cmp r1, 0
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// bz L1
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//
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// If the "sub" instruction all ready sets (or could be modified to set) the
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// same flag that the "cmp" instruction sets and that "bz" uses, then we can
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// eliminate the "cmp" instruction.
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//
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// Another instance, in this code:
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//
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// sub r1, r3 | sub r1, imm
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// cmp r3, r1 or cmp r1, r3 | cmp r1, imm
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// bge L1
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//
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// If the branch instruction can use flag from "sub", then we can replace
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// "sub" with "subs" and eliminate the "cmp" instruction.
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//
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// - Optimize Loads:
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//
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// Loads that can be folded into a later instruction. A load is foldable
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// if it loads to virtual registers and the virtual register defined has
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// a single use.
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//
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// - Optimize Copies and Bitcast (more generally, target specific copies):
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//
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// Rewrite copies and bitcasts to avoid cross register bank copies
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// when possible.
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// E.g., Consider the following example, where capital and lower
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// letters denote different register file:
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// b = copy A <-- cross-bank copy
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// C = copy b <-- cross-bank copy
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// =>
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// b = copy A <-- cross-bank copy
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// C = copy A <-- same-bank copy
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//
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// E.g., for bitcast:
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// b = bitcast A <-- cross-bank copy
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// C = bitcast b <-- cross-bank copy
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// =>
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// b = bitcast A <-- cross-bank copy
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// C = copy A <-- same-bank copy
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "peephole-opt"
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// Optimize Extensions
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static cl::opt<bool>
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Aggressive("aggressive-ext-opt", cl::Hidden,
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cl::desc("Aggressive extension optimization"));
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static cl::opt<bool>
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DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
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cl::desc("Disable the peephole optimizer"));
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static cl::opt<bool>
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DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
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cl::desc("Disable advanced copy optimization"));
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STATISTIC(NumReuse, "Number of extension results reused");
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STATISTIC(NumCmps, "Number of compares eliminated");
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STATISTIC(NumImmFold, "Number of move immediate folded");
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STATISTIC(NumLoadFold, "Number of loads folded");
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STATISTIC(NumSelects, "Number of selects optimized");
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STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
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STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
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namespace {
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class PeepholeOptimizer : public MachineFunctionPass {
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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MachineDominatorTree *DT; // Machine dominator tree
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public:
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static char ID; // Pass identification
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PeepholeOptimizer() : MachineFunctionPass(ID) {
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initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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if (Aggressive) {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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}
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private:
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bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
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bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSetImpl<MachineInstr*> &LocalMIs);
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bool optimizeSelect(MachineInstr *MI);
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bool optimizeCopyOrBitcast(MachineInstr *MI);
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bool optimizeCoalescableCopy(MachineInstr *MI);
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bool optimizeUncoalescableCopy(MachineInstr *MI,
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SmallPtrSetImpl<MachineInstr *> &LocalMIs);
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bool findNextSource(unsigned &Reg, unsigned &SubReg);
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bool isMoveImmediate(MachineInstr *MI,
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SmallSet<unsigned, 4> &ImmDefRegs,
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DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
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bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallSet<unsigned, 4> &ImmDefRegs,
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DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
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bool isLoadFoldable(MachineInstr *MI,
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SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
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/// \brief Check whether \p MI is understood by the register coalescer
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/// but may require some rewriting.
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bool isCoalescableCopy(const MachineInstr &MI) {
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// SubregToRegs are not interesting, because they are already register
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// coalescer friendly.
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return MI.isCopy() || (!DisableAdvCopyOpt &&
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(MI.isRegSequence() || MI.isInsertSubreg() ||
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MI.isExtractSubreg()));
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}
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/// \brief Check whether \p MI is a copy like instruction that is
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/// not recognized by the register coalescer.
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bool isUncoalescableCopy(const MachineInstr &MI) {
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return MI.isBitcast() ||
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(!DisableAdvCopyOpt &&
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(MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
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MI.isExtractSubregLike()));
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}
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};
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/// \brief Helper class to track the possible sources of a value defined by
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/// a (chain of) copy related instructions.
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/// Given a definition (instruction and definition index), this class
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/// follows the use-def chain to find successive suitable sources.
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/// The given source can be used to rewrite the definition into
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/// def = COPY src.
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///
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/// For instance, let us consider the following snippet:
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/// v0 =
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/// v2 = INSERT_SUBREG v1, v0, sub0
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/// def = COPY v2.sub0
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///
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/// Using a ValueTracker for def = COPY v2.sub0 will give the following
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/// suitable sources:
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/// v2.sub0 and v0.
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/// Then, def can be rewritten into def = COPY v0.
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class ValueTracker {
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private:
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/// The current point into the use-def chain.
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const MachineInstr *Def;
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/// The index of the definition in Def.
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unsigned DefIdx;
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/// The sub register index of the definition.
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unsigned DefSubReg;
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/// The register where the value can be found.
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unsigned Reg;
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/// Specifiy whether or not the value tracking looks through
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/// complex instructions. When this is false, the value tracker
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/// bails on everything that is not a copy or a bitcast.
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///
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/// Note: This could have been implemented as a specialized version of
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/// the ValueTracker class but that would have complicated the code of
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/// the users of this class.
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bool UseAdvancedTracking;
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/// MachineRegisterInfo used to perform tracking.
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const MachineRegisterInfo &MRI;
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/// Optional TargetInstrInfo used to perform some complex
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/// tracking.
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const TargetInstrInfo *TII;
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/// \brief Dispatcher to the right underlying implementation of
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/// getNextSource.
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bool getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for Copy instructions.
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bool getNextSourceFromCopy(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for Bitcast instructions.
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bool getNextSourceFromBitcast(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for RegSequence
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/// instructions.
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bool getNextSourceFromRegSequence(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for InsertSubreg
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/// instructions.
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bool getNextSourceFromInsertSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for ExtractSubreg
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/// instructions.
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bool getNextSourceFromExtractSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for SubregToReg
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/// instructions.
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bool getNextSourceFromSubregToReg(unsigned &SrcReg, unsigned &SrcSubReg);
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public:
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/// \brief Create a ValueTracker instance for the value defined by \p Reg.
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/// \p DefSubReg represents the sub register index the value tracker will
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/// track. It does not need to match the sub register index used in the
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/// definition of \p Reg.
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/// \p UseAdvancedTracking specifies whether or not the value tracker looks
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/// through complex instructions. By default (false), it handles only copy
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/// and bitcast instructions.
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/// If \p Reg is a physical register, a value tracker constructed with
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/// this constructor will not find any alternative source.
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/// Indeed, when \p Reg is a physical register that constructor does not
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/// know which definition of \p Reg it should track.
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/// Use the next constructor to track a physical register.
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ValueTracker(unsigned Reg, unsigned DefSubReg,
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const MachineRegisterInfo &MRI,
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bool UseAdvancedTracking = false,
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const TargetInstrInfo *TII = nullptr)
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: Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
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UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
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if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
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Def = MRI.getVRegDef(Reg);
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DefIdx = MRI.def_begin(Reg).getOperandNo();
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}
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}
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/// \brief Create a ValueTracker instance for the value defined by
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/// the pair \p MI, \p DefIdx.
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/// Unlike the other constructor, the value tracker produced by this one
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/// may be able to find a new source when the definition is a physical
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/// register.
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/// This could be useful to rewrite target specific instructions into
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/// generic copy instructions.
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ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
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const MachineRegisterInfo &MRI,
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bool UseAdvancedTracking = false,
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const TargetInstrInfo *TII = nullptr)
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: Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
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UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
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assert(DefIdx < Def->getDesc().getNumDefs() &&
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Def->getOperand(DefIdx).isReg() && "Invalid definition");
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Reg = Def->getOperand(DefIdx).getReg();
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}
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/// \brief Following the use-def chain, get the next available source
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/// for the tracked value.
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/// When the returned value is not nullptr, \p SrcReg gives the register
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/// that contain the tracked value.
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/// \note The sub register index returned in \p SrcSubReg must be used
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/// on \p SrcReg to access the actual value.
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/// \return Unless the returned value is nullptr (i.e., no source found),
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/// \p SrcReg gives the register of the next source used in the returned
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/// instruction and \p SrcSubReg the sub-register index to be used on that
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/// source to get the tracked value. When nullptr is returned, no
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/// alternative source has been found.
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const MachineInstr *getNextSource(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Get the last register where the initial value can be found.
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/// Initially this is the register of the definition.
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/// Then, after each successful call to getNextSource, this is the
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/// register of the last source.
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unsigned getReg() const { return Reg; }
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};
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}
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char PeepholeOptimizer::ID = 0;
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char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
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INITIALIZE_PASS_BEGIN(PeepholeOptimizer, "peephole-opts",
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"Peephole Optimizations", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
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"Peephole Optimizations", false, false)
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/// optimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
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/// a single register and writes a single register and it does not modify the
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/// source, and if the source value is preserved as a sub-register of the
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/// result, then replace all reachable uses of the source with the subreg of the
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/// result.
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///
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/// Do not generate an EXTRACT that is used only in a debug use, as this changes
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/// the code. Since this code does not currently share EXTRACTs, just ignore all
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/// debug uses.
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bool PeepholeOptimizer::
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optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
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unsigned SrcReg, DstReg, SubIdx;
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if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
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return false;
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if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
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TargetRegisterInfo::isPhysicalRegister(SrcReg))
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return false;
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if (MRI->hasOneNonDBGUse(SrcReg))
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// No other uses.
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return false;
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// Ensure DstReg can get a register class that actually supports
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// sub-registers. Don't change the class until we commit.
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const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
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DstRC = TM->getSubtargetImpl()->getRegisterInfo()->getSubClassWithSubReg(
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DstRC, SubIdx);
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if (!DstRC)
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return false;
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// The ext instr may be operating on a sub-register of SrcReg as well.
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// PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
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// register.
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// If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
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// SrcReg:SubIdx should be replaced.
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bool UseSrcSubIdx =
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TM->getSubtargetImpl()->getRegisterInfo()->getSubClassWithSubReg(
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MRI->getRegClass(SrcReg), SubIdx) != nullptr;
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// The source has other uses. See if we can replace the other uses with use of
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// the result of the extension.
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SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
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for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
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ReachedBBs.insert(UI.getParent());
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// Uses that are in the same BB of uses of the result of the instruction.
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SmallVector<MachineOperand*, 8> Uses;
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// Uses that the result of the instruction can reach.
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SmallVector<MachineOperand*, 8> ExtendedUses;
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bool ExtendLife = true;
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for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
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MachineInstr *UseMI = UseMO.getParent();
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if (UseMI == MI)
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continue;
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if (UseMI->isPHI()) {
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ExtendLife = false;
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continue;
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}
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// Only accept uses of SrcReg:SubIdx.
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if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
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continue;
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// It's an error to translate this:
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//
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// %reg1025 = <sext> %reg1024
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// ...
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// %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
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//
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// into this:
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//
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// %reg1025 = <sext> %reg1024
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// ...
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// %reg1027 = COPY %reg1025:4
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// %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
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//
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// The problem here is that SUBREG_TO_REG is there to assert that an
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// implicit zext occurs. It doesn't insert a zext instruction. If we allow
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// the COPY here, it will give us the value after the <sext>, not the
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// original value of %reg1024 before <sext>.
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if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
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continue;
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (UseMBB == MBB) {
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// Local uses that come after the extension.
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if (!LocalMIs.count(UseMI))
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Uses.push_back(&UseMO);
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} else if (ReachedBBs.count(UseMBB)) {
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// Non-local uses where the result of the extension is used. Always
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// replace these unless it's a PHI.
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Uses.push_back(&UseMO);
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} else if (Aggressive && DT->dominates(MBB, UseMBB)) {
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// We may want to extend the live range of the extension result in order
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// to replace these uses.
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ExtendedUses.push_back(&UseMO);
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} else {
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// Both will be live out of the def MBB anyway. Don't extend live range of
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// the extension result.
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ExtendLife = false;
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break;
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}
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}
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if (ExtendLife && !ExtendedUses.empty())
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// Extend the liveness of the extension result.
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std::copy(ExtendedUses.begin(), ExtendedUses.end(),
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std::back_inserter(Uses));
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// Now replace all uses.
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bool Changed = false;
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if (!Uses.empty()) {
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SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
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// Look for PHI uses of the extended result, we don't want to extend the
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// liveness of a PHI input. It breaks all kinds of assumptions down
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// stream. A PHI use is expected to be the kill of its source values.
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for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
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if (UI.isPHI())
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PHIBBs.insert(UI.getParent());
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const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
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for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
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MachineOperand *UseMO = Uses[i];
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MachineInstr *UseMI = UseMO->getParent();
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (PHIBBs.count(UseMBB))
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continue;
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// About to add uses of DstReg, clear DstReg's kill flags.
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if (!Changed) {
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MRI->clearKillFlags(DstReg);
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MRI->constrainRegClass(DstReg, DstRC);
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}
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unsigned NewVR = MRI->createVirtualRegister(RC);
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MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
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TII->get(TargetOpcode::COPY), NewVR)
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.addReg(DstReg, 0, SubIdx);
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// SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
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if (UseSrcSubIdx) {
|
|
Copy->getOperand(0).setSubReg(SubIdx);
|
|
Copy->getOperand(0).setIsUndef();
|
|
}
|
|
UseMO->setReg(NewVR);
|
|
++NumReuse;
|
|
Changed = true;
|
|
}
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
/// optimizeCmpInstr - If the instruction is a compare and the previous
|
|
/// instruction it's comparing against all ready sets (or could be modified to
|
|
/// set) the same flag as the compare, then we can remove the comparison and use
|
|
/// the flag from the previous instruction.
|
|
bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) {
|
|
// If this instruction is a comparison against zero and isn't comparing a
|
|
// physical register, we can try to optimize it.
|
|
unsigned SrcReg, SrcReg2;
|
|
int CmpMask, CmpValue;
|
|
if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
|
|
TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
|
|
(SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
|
|
return false;
|
|
|
|
// Attempt to optimize the comparison instruction.
|
|
if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
|
|
++NumCmps;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// Optimize a select instruction.
|
|
bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI) {
|
|
unsigned TrueOp = 0;
|
|
unsigned FalseOp = 0;
|
|
bool Optimizable = false;
|
|
SmallVector<MachineOperand, 4> Cond;
|
|
if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
|
|
return false;
|
|
if (!Optimizable)
|
|
return false;
|
|
if (!TII->optimizeSelect(MI))
|
|
return false;
|
|
MI->eraseFromParent();
|
|
++NumSelects;
|
|
return true;
|
|
}
|
|
|
|
/// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
|
|
/// share the same register file.
|
|
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
|
|
const TargetRegisterClass *DefRC,
|
|
unsigned DefSubReg,
|
|
const TargetRegisterClass *SrcRC,
|
|
unsigned SrcSubReg) {
|
|
// Same register class.
|
|
if (DefRC == SrcRC)
|
|
return true;
|
|
|
|
// Both operands are sub registers. Check if they share a register class.
|
|
unsigned SrcIdx, DefIdx;
|
|
if (SrcSubReg && DefSubReg)
|
|
return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
|
|
SrcIdx, DefIdx) != nullptr;
|
|
// At most one of the register is a sub register, make it Src to avoid
|
|
// duplicating the test.
|
|
if (!SrcSubReg) {
|
|
std::swap(DefSubReg, SrcSubReg);
|
|
std::swap(DefRC, SrcRC);
|
|
}
|
|
|
|
// One of the register is a sub register, check if we can get a superclass.
|
|
if (SrcSubReg)
|
|
return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
|
|
// Plain copy.
|
|
return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
|
|
}
|
|
|
|
/// \brief Try to find the next source that share the same register file
|
|
/// for the value defined by \p Reg and \p SubReg.
|
|
/// When true is returned, \p Reg and \p SubReg are updated with the
|
|
/// register number and sub-register index of the new source.
|
|
/// \return False if no alternative sources are available. True otherwise.
|
|
bool PeepholeOptimizer::findNextSource(unsigned &Reg, unsigned &SubReg) {
|
|
// Do not try to find a new source for a physical register.
|
|
// So far we do not have any motivating example for doing that.
|
|
// Thus, instead of maintaining untested code, we will revisit that if
|
|
// that changes at some point.
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
return false;
|
|
|
|
const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
|
|
unsigned DefSubReg = SubReg;
|
|
|
|
unsigned Src;
|
|
unsigned SrcSubReg;
|
|
bool ShouldRewrite = false;
|
|
const TargetRegisterInfo &TRI = *TM->getSubtargetImpl()->getRegisterInfo();
|
|
|
|
// Follow the chain of copies until we reach the top of the use-def chain
|
|
// or find a more suitable source.
|
|
ValueTracker ValTracker(Reg, DefSubReg, *MRI, !DisableAdvCopyOpt, TII);
|
|
do {
|
|
unsigned CopySrcReg, CopySrcSubReg;
|
|
if (!ValTracker.getNextSource(CopySrcReg, CopySrcSubReg))
|
|
break;
|
|
Src = CopySrcReg;
|
|
SrcSubReg = CopySrcSubReg;
|
|
|
|
// Do not extend the live-ranges of physical registers as they add
|
|
// constraints to the register allocator.
|
|
// Moreover, if we want to extend the live-range of a physical register,
|
|
// unlike SSA virtual register, we will have to check that they are not
|
|
// redefine before the related use.
|
|
if (TargetRegisterInfo::isPhysicalRegister(Src))
|
|
break;
|
|
|
|
const TargetRegisterClass *SrcRC = MRI->getRegClass(Src);
|
|
|
|
// If this source does not incur a cross register bank copy, use it.
|
|
ShouldRewrite = shareSameRegisterFile(TRI, DefRC, DefSubReg, SrcRC,
|
|
SrcSubReg);
|
|
} while (!ShouldRewrite);
|
|
|
|
// If we did not find a more suitable source, there is nothing to optimize.
|
|
if (!ShouldRewrite || Src == Reg)
|
|
return false;
|
|
|
|
Reg = Src;
|
|
SubReg = SrcSubReg;
|
|
return true;
|
|
}
|
|
|
|
namespace {
|
|
/// \brief Helper class to rewrite the arguments of a copy-like instruction.
|
|
class CopyRewriter {
|
|
protected:
|
|
/// The copy-like instruction.
|
|
MachineInstr &CopyLike;
|
|
/// The index of the source being rewritten.
|
|
unsigned CurrentSrcIdx;
|
|
|
|
public:
|
|
CopyRewriter(MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {}
|
|
|
|
virtual ~CopyRewriter() {}
|
|
|
|
/// \brief Get the next rewritable source (SrcReg, SrcSubReg) and
|
|
/// the related value that it affects (TrackReg, TrackSubReg).
|
|
/// A source is considered rewritable if its register class and the
|
|
/// register class of the related TrackReg may not be register
|
|
/// coalescer friendly. In other words, given a copy-like instruction
|
|
/// not all the arguments may be returned at rewritable source, since
|
|
/// some arguments are none to be register coalescer friendly.
|
|
///
|
|
/// Each call of this method moves the current source to the next
|
|
/// rewritable source.
|
|
/// For instance, let CopyLike be the instruction to rewrite.
|
|
/// CopyLike has one definition and one source:
|
|
/// dst.dstSubIdx = CopyLike src.srcSubIdx.
|
|
///
|
|
/// The first call will give the first rewritable source, i.e.,
|
|
/// the only source this instruction has:
|
|
/// (SrcReg, SrcSubReg) = (src, srcSubIdx).
|
|
/// This source defines the whole definition, i.e.,
|
|
/// (TrackReg, TrackSubReg) = (dst, dstSubIdx).
|
|
///
|
|
/// The second and subsequent calls will return false, has there is only one
|
|
/// rewritable source.
|
|
///
|
|
/// \return True if a rewritable source has been found, false otherwise.
|
|
/// The output arguments are valid if and only if true is returned.
|
|
virtual bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
unsigned &TrackReg,
|
|
unsigned &TrackSubReg) {
|
|
// If CurrentSrcIdx == 1, this means this function has already been
|
|
// called once. CopyLike has one defintiion and one argument, thus,
|
|
// there is nothing else to rewrite.
|
|
if (!CopyLike.isCopy() || CurrentSrcIdx == 1)
|
|
return false;
|
|
// This is the first call to getNextRewritableSource.
|
|
// Move the CurrentSrcIdx to remember that we made that call.
|
|
CurrentSrcIdx = 1;
|
|
// The rewritable source is the argument.
|
|
const MachineOperand &MOSrc = CopyLike.getOperand(1);
|
|
SrcReg = MOSrc.getReg();
|
|
SrcSubReg = MOSrc.getSubReg();
|
|
// What we track are the alternative sources of the definition.
|
|
const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
TrackReg = MODef.getReg();
|
|
TrackSubReg = MODef.getSubReg();
|
|
return true;
|
|
}
|
|
|
|
/// \brief Rewrite the current source with \p NewReg and \p NewSubReg
|
|
/// if possible.
|
|
/// \return True if the rewritting was possible, false otherwise.
|
|
virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) {
|
|
if (!CopyLike.isCopy() || CurrentSrcIdx != 1)
|
|
return false;
|
|
MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
|
|
MOSrc.setReg(NewReg);
|
|
MOSrc.setSubReg(NewSubReg);
|
|
return true;
|
|
}
|
|
};
|
|
|
|
/// \brief Specialized rewriter for INSERT_SUBREG instruction.
|
|
class InsertSubregRewriter : public CopyRewriter {
|
|
public:
|
|
InsertSubregRewriter(MachineInstr &MI) : CopyRewriter(MI) {
|
|
assert(MI.isInsertSubreg() && "Invalid instruction");
|
|
}
|
|
|
|
/// \brief See CopyRewriter::getNextRewritableSource.
|
|
/// Here CopyLike has the following form:
|
|
/// dst = INSERT_SUBREG Src1, Src2.src2SubIdx, subIdx.
|
|
/// Src1 has the same register class has dst, hence, there is
|
|
/// nothing to rewrite.
|
|
/// Src2.src2SubIdx, may not be register coalescer friendly.
|
|
/// Therefore, the first call to this method returns:
|
|
/// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
|
|
/// (TrackReg, TrackSubReg) = (dst, subIdx).
|
|
///
|
|
/// Subsequence calls will return false.
|
|
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
unsigned &TrackReg,
|
|
unsigned &TrackSubReg) override {
|
|
// If we already get the only source we can rewrite, return false.
|
|
if (CurrentSrcIdx == 2)
|
|
return false;
|
|
// We are looking at v2 = INSERT_SUBREG v0, v1, sub0.
|
|
CurrentSrcIdx = 2;
|
|
const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
|
|
SrcReg = MOInsertedReg.getReg();
|
|
SrcSubReg = MOInsertedReg.getSubReg();
|
|
const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
|
|
// We want to track something that is compatible with the
|
|
// partial definition.
|
|
TrackReg = MODef.getReg();
|
|
if (MODef.getSubReg())
|
|
// Bails if we have to compose sub-register indices.
|
|
return false;
|
|
TrackSubReg = (unsigned)CopyLike.getOperand(3).getImm();
|
|
return true;
|
|
}
|
|
bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
|
|
if (CurrentSrcIdx != 2)
|
|
return false;
|
|
// We are rewriting the inserted reg.
|
|
MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
|
|
MO.setReg(NewReg);
|
|
MO.setSubReg(NewSubReg);
|
|
return true;
|
|
}
|
|
};
|
|
|
|
/// \brief Specialized rewriter for EXTRACT_SUBREG instruction.
|
|
class ExtractSubregRewriter : public CopyRewriter {
|
|
const TargetInstrInfo &TII;
|
|
|
|
public:
|
|
ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
|
|
: CopyRewriter(MI), TII(TII) {
|
|
assert(MI.isExtractSubreg() && "Invalid instruction");
|
|
}
|
|
|
|
/// \brief See CopyRewriter::getNextRewritableSource.
|
|
/// Here CopyLike has the following form:
|
|
/// dst.dstSubIdx = EXTRACT_SUBREG Src, subIdx.
|
|
/// There is only one rewritable source: Src.subIdx,
|
|
/// which defines dst.dstSubIdx.
|
|
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
unsigned &TrackReg,
|
|
unsigned &TrackSubReg) override {
|
|
// If we already get the only source we can rewrite, return false.
|
|
if (CurrentSrcIdx == 1)
|
|
return false;
|
|
// We are looking at v1 = EXTRACT_SUBREG v0, sub0.
|
|
CurrentSrcIdx = 1;
|
|
const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
|
|
SrcReg = MOExtractedReg.getReg();
|
|
// If we have to compose sub-register indices, bails out.
|
|
if (MOExtractedReg.getSubReg())
|
|
return false;
|
|
|
|
SrcSubReg = CopyLike.getOperand(2).getImm();
|
|
|
|
// We want to track something that is compatible with the definition.
|
|
const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
TrackReg = MODef.getReg();
|
|
TrackSubReg = MODef.getSubReg();
|
|
return true;
|
|
}
|
|
|
|
bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
|
|
// The only source we can rewrite is the input register.
|
|
if (CurrentSrcIdx != 1)
|
|
return false;
|
|
|
|
CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
|
|
|
|
// If we find a source that does not require to extract something,
|
|
// rewrite the operation with a copy.
|
|
if (!NewSubReg) {
|
|
// Move the current index to an invalid position.
|
|
// We do not want another call to this method to be able
|
|
// to do any change.
|
|
CurrentSrcIdx = -1;
|
|
// Rewrite the operation as a COPY.
|
|
// Get rid of the sub-register index.
|
|
CopyLike.RemoveOperand(2);
|
|
// Morph the operation into a COPY.
|
|
CopyLike.setDesc(TII.get(TargetOpcode::COPY));
|
|
return true;
|
|
}
|
|
CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
|
|
return true;
|
|
}
|
|
};
|
|
|
|
/// \brief Specialized rewriter for REG_SEQUENCE instruction.
|
|
class RegSequenceRewriter : public CopyRewriter {
|
|
public:
|
|
RegSequenceRewriter(MachineInstr &MI) : CopyRewriter(MI) {
|
|
assert(MI.isRegSequence() && "Invalid instruction");
|
|
}
|
|
|
|
/// \brief See CopyRewriter::getNextRewritableSource.
|
|
/// Here CopyLike has the following form:
|
|
/// dst = REG_SEQUENCE Src1.src1SubIdx, subIdx1, Src2.src2SubIdx, subIdx2.
|
|
/// Each call will return a different source, walking all the available
|
|
/// source.
|
|
///
|
|
/// The first call returns:
|
|
/// (SrcReg, SrcSubReg) = (Src1, src1SubIdx).
|
|
/// (TrackReg, TrackSubReg) = (dst, subIdx1).
|
|
///
|
|
/// The second call returns:
|
|
/// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
|
|
/// (TrackReg, TrackSubReg) = (dst, subIdx2).
|
|
///
|
|
/// And so on, until all the sources have been traversed, then
|
|
/// it returns false.
|
|
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
unsigned &TrackReg,
|
|
unsigned &TrackSubReg) override {
|
|
// We are looking at v0 = REG_SEQUENCE v1, sub1, v2, sub2, etc.
|
|
|
|
// If this is the first call, move to the first argument.
|
|
if (CurrentSrcIdx == 0) {
|
|
CurrentSrcIdx = 1;
|
|
} else {
|
|
// Otherwise, move to the next argument and check that it is valid.
|
|
CurrentSrcIdx += 2;
|
|
if (CurrentSrcIdx >= CopyLike.getNumOperands())
|
|
return false;
|
|
}
|
|
const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
|
|
SrcReg = MOInsertedReg.getReg();
|
|
// If we have to compose sub-register indices, bails out.
|
|
if ((SrcSubReg = MOInsertedReg.getSubReg()))
|
|
return false;
|
|
|
|
// We want to track something that is compatible with the related
|
|
// partial definition.
|
|
TrackSubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
|
|
|
|
const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
TrackReg = MODef.getReg();
|
|
// If we have to compose sub-registers, bails.
|
|
return MODef.getSubReg() == 0;
|
|
}
|
|
|
|
bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
|
|
// We cannot rewrite out of bound operands.
|
|
// Moreover, rewritable sources are at odd positions.
|
|
if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
|
|
return false;
|
|
|
|
MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
|
|
MO.setReg(NewReg);
|
|
MO.setSubReg(NewSubReg);
|
|
return true;
|
|
}
|
|
};
|
|
} // End namespace.
|
|
|
|
/// \brief Get the appropriated CopyRewriter for \p MI.
|
|
/// \return A pointer to a dynamically allocated CopyRewriter or nullptr
|
|
/// if no rewriter works for \p MI.
|
|
static CopyRewriter *getCopyRewriter(MachineInstr &MI,
|
|
const TargetInstrInfo &TII) {
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
return nullptr;
|
|
case TargetOpcode::COPY:
|
|
return new CopyRewriter(MI);
|
|
case TargetOpcode::INSERT_SUBREG:
|
|
return new InsertSubregRewriter(MI);
|
|
case TargetOpcode::EXTRACT_SUBREG:
|
|
return new ExtractSubregRewriter(MI, TII);
|
|
case TargetOpcode::REG_SEQUENCE:
|
|
return new RegSequenceRewriter(MI);
|
|
}
|
|
llvm_unreachable(nullptr);
|
|
}
|
|
|
|
/// \brief Optimize generic copy instructions to avoid cross
|
|
/// register bank copy. The optimization looks through a chain of
|
|
/// copies and tries to find a source that has a compatible register
|
|
/// class.
|
|
/// Two register classes are considered to be compatible if they share
|
|
/// the same register bank.
|
|
/// New copies issued by this optimization are register allocator
|
|
/// friendly. This optimization does not remove any copy as it may
|
|
/// overconstraint the register allocator, but replaces some operands
|
|
/// when possible.
|
|
/// \pre isCoalescableCopy(*MI) is true.
|
|
/// \return True, when \p MI has been rewritten. False otherwise.
|
|
bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr *MI) {
|
|
assert(MI && isCoalescableCopy(*MI) && "Invalid argument");
|
|
assert(MI->getDesc().getNumDefs() == 1 &&
|
|
"Coalescer can understand multiple defs?!");
|
|
const MachineOperand &MODef = MI->getOperand(0);
|
|
// Do not rewrite physical definitions.
|
|
if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
|
|
return false;
|
|
|
|
bool Changed = false;
|
|
// Get the right rewriter for the current copy.
|
|
std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII));
|
|
// If none exists, bails out.
|
|
if (!CpyRewriter)
|
|
return false;
|
|
// Rewrite each rewritable source.
|
|
unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg;
|
|
while (CpyRewriter->getNextRewritableSource(SrcReg, SrcSubReg, TrackReg,
|
|
TrackSubReg)) {
|
|
unsigned NewSrc = TrackReg;
|
|
unsigned NewSubReg = TrackSubReg;
|
|
// Try to find a more suitable source.
|
|
// If we failed to do so, or get the actual source,
|
|
// move to the next source.
|
|
if (!findNextSource(NewSrc, NewSubReg) || SrcReg == NewSrc)
|
|
continue;
|
|
// Rewrite source.
|
|
if (CpyRewriter->RewriteCurrentSource(NewSrc, NewSubReg)) {
|
|
// We may have extended the live-range of NewSrc, account for that.
|
|
MRI->clearKillFlags(NewSrc);
|
|
Changed = true;
|
|
}
|
|
}
|
|
// TODO: We could have a clean-up method to tidy the instruction.
|
|
// E.g., v0 = INSERT_SUBREG v1, v1.sub0, sub0
|
|
// => v0 = COPY v1
|
|
// Currently we haven't seen motivating example for that and we
|
|
// want to avoid untested code.
|
|
NumRewrittenCopies += Changed == true;
|
|
return Changed;
|
|
}
|
|
|
|
/// \brief Optimize copy-like instructions to create
|
|
/// register coalescer friendly instruction.
|
|
/// The optimization tries to kill-off the \p MI by looking
|
|
/// through a chain of copies to find a source that has a compatible
|
|
/// register class.
|
|
/// If such a source is found, it replace \p MI by a generic COPY
|
|
/// operation.
|
|
/// \pre isUncoalescableCopy(*MI) is true.
|
|
/// \return True, when \p MI has been optimized. In that case, \p MI has
|
|
/// been removed from its parent.
|
|
/// All COPY instructions created, are inserted in \p LocalMIs.
|
|
bool PeepholeOptimizer::optimizeUncoalescableCopy(
|
|
MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
|
|
assert(MI && isUncoalescableCopy(*MI) && "Invalid argument");
|
|
|
|
// Check if we can rewrite all the values defined by this instruction.
|
|
SmallVector<
|
|
std::pair<TargetInstrInfo::RegSubRegPair, TargetInstrInfo::RegSubRegPair>,
|
|
4> RewritePairs;
|
|
for (const MachineOperand &MODef : MI->defs()) {
|
|
if (MODef.isDead())
|
|
// We can ignore those.
|
|
continue;
|
|
|
|
// If a physical register is here, this is probably for a good reason.
|
|
// Do not rewrite that.
|
|
if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
|
|
return false;
|
|
|
|
// If we do not know how to rewrite this definition, there is no point
|
|
// in trying to kill this instruction.
|
|
TargetInstrInfo::RegSubRegPair Def(MODef.getReg(), MODef.getSubReg());
|
|
TargetInstrInfo::RegSubRegPair Src = Def;
|
|
if (!findNextSource(Src.Reg, Src.SubReg))
|
|
return false;
|
|
RewritePairs.push_back(std::make_pair(Def, Src));
|
|
}
|
|
// The change is possible for all defs, do it.
|
|
for (const auto &PairDefSrc : RewritePairs) {
|
|
const auto &Def = PairDefSrc.first;
|
|
const auto &Src = PairDefSrc.second;
|
|
// Rewrite the "copy" in a way the register coalescer understands.
|
|
assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
|
|
"We do not rewrite physical registers");
|
|
const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
|
|
unsigned NewVR = MRI->createVirtualRegister(DefRC);
|
|
MachineInstr *NewCopy = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY),
|
|
NewVR).addReg(Src.Reg, 0, Src.SubReg);
|
|
NewCopy->getOperand(0).setSubReg(Def.SubReg);
|
|
if (Def.SubReg)
|
|
NewCopy->getOperand(0).setIsUndef();
|
|
LocalMIs.insert(NewCopy);
|
|
MRI->replaceRegWith(Def.Reg, NewVR);
|
|
MRI->clearKillFlags(NewVR);
|
|
// We extended the lifetime of Src.
|
|
// Clear the kill flags to account for that.
|
|
MRI->clearKillFlags(Src.Reg);
|
|
}
|
|
// MI is now dead.
|
|
MI->eraseFromParent();
|
|
++NumUncoalescableCopies;
|
|
return true;
|
|
}
|
|
|
|
/// isLoadFoldable - Check whether MI is a candidate for folding into a later
|
|
/// instruction. We only fold loads to virtual registers and the virtual
|
|
/// register defined has a single use.
|
|
bool PeepholeOptimizer::isLoadFoldable(
|
|
MachineInstr *MI,
|
|
SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
|
|
if (!MI->canFoldAsLoad() || !MI->mayLoad())
|
|
return false;
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
if (MCID.getNumDefs() != 1)
|
|
return false;
|
|
|
|
unsigned Reg = MI->getOperand(0).getReg();
|
|
// To reduce compilation time, we check MRI->hasOneNonDBGUse when inserting
|
|
// loads. It should be checked when processing uses of the load, since
|
|
// uses can be removed during peephole.
|
|
if (!MI->getOperand(0).getSubReg() &&
|
|
TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
MRI->hasOneNonDBGUse(Reg)) {
|
|
FoldAsLoadDefCandidates.insert(Reg);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
|
|
SmallSet<unsigned, 4> &ImmDefRegs,
|
|
DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
if (!MI->isMoveImmediate())
|
|
return false;
|
|
if (MCID.getNumDefs() != 1)
|
|
return false;
|
|
unsigned Reg = MI->getOperand(0).getReg();
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
ImmDefMIs.insert(std::make_pair(Reg, MI));
|
|
ImmDefRegs.insert(Reg);
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// foldImmediate - Try folding register operands that are defined by move
|
|
/// immediate instructions, i.e. a trivial constant folding optimization, if
|
|
/// and only if the def and use are in the same BB.
|
|
bool PeepholeOptimizer::foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
|
|
SmallSet<unsigned, 4> &ImmDefRegs,
|
|
DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
|
|
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || MO.isDef())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
continue;
|
|
if (ImmDefRegs.count(Reg) == 0)
|
|
continue;
|
|
DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
|
|
assert(II != ImmDefMIs.end());
|
|
if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
|
|
++NumImmFold;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
|
|
if (skipOptnoneFunction(*MF.getFunction()))
|
|
return false;
|
|
|
|
DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
|
|
DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
|
|
|
|
if (DisablePeephole)
|
|
return false;
|
|
|
|
TM = &MF.getTarget();
|
|
TII = TM->getSubtargetImpl()->getInstrInfo();
|
|
MRI = &MF.getRegInfo();
|
|
DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : nullptr;
|
|
|
|
bool Changed = false;
|
|
|
|
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
|
|
MachineBasicBlock *MBB = &*I;
|
|
|
|
bool SeenMoveImm = false;
|
|
SmallPtrSet<MachineInstr*, 16> LocalMIs;
|
|
SmallSet<unsigned, 4> ImmDefRegs;
|
|
DenseMap<unsigned, MachineInstr*> ImmDefMIs;
|
|
SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
|
|
|
|
for (MachineBasicBlock::iterator
|
|
MII = I->begin(), MIE = I->end(); MII != MIE; ) {
|
|
MachineInstr *MI = &*MII;
|
|
// We may be erasing MI below, increment MII now.
|
|
++MII;
|
|
LocalMIs.insert(MI);
|
|
|
|
// Skip debug values. They should not affect this peephole optimization.
|
|
if (MI->isDebugValue())
|
|
continue;
|
|
|
|
// If there exists an instruction which belongs to the following
|
|
// categories, we will discard the load candidates.
|
|
if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() ||
|
|
MI->isKill() || MI->isInlineAsm() ||
|
|
MI->hasUnmodeledSideEffects()) {
|
|
FoldAsLoadDefCandidates.clear();
|
|
continue;
|
|
}
|
|
if (MI->mayStore() || MI->isCall())
|
|
FoldAsLoadDefCandidates.clear();
|
|
|
|
if ((isUncoalescableCopy(*MI) &&
|
|
optimizeUncoalescableCopy(MI, LocalMIs)) ||
|
|
(MI->isCompare() && optimizeCmpInstr(MI, MBB)) ||
|
|
(MI->isSelect() && optimizeSelect(MI))) {
|
|
// MI is deleted.
|
|
LocalMIs.erase(MI);
|
|
Changed = true;
|
|
continue;
|
|
}
|
|
|
|
if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(MI)) {
|
|
// MI is just rewritten.
|
|
Changed = true;
|
|
continue;
|
|
}
|
|
|
|
if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
|
|
SeenMoveImm = true;
|
|
} else {
|
|
Changed |= optimizeExtInstr(MI, MBB, LocalMIs);
|
|
// optimizeExtInstr might have created new instructions after MI
|
|
// and before the already incremented MII. Adjust MII so that the
|
|
// next iteration sees the new instructions.
|
|
MII = MI;
|
|
++MII;
|
|
if (SeenMoveImm)
|
|
Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
|
|
}
|
|
|
|
// Check whether MI is a load candidate for folding into a later
|
|
// instruction. If MI is not a candidate, check whether we can fold an
|
|
// earlier load into MI.
|
|
if (!isLoadFoldable(MI, FoldAsLoadDefCandidates) &&
|
|
!FoldAsLoadDefCandidates.empty()) {
|
|
const MCInstrDesc &MIDesc = MI->getDesc();
|
|
for (unsigned i = MIDesc.getNumDefs(); i != MIDesc.getNumOperands();
|
|
++i) {
|
|
const MachineOperand &MOp = MI->getOperand(i);
|
|
if (!MOp.isReg())
|
|
continue;
|
|
unsigned FoldAsLoadDefReg = MOp.getReg();
|
|
if (FoldAsLoadDefCandidates.count(FoldAsLoadDefReg)) {
|
|
// We need to fold load after optimizeCmpInstr, since
|
|
// optimizeCmpInstr can enable folding by converting SUB to CMP.
|
|
// Save FoldAsLoadDefReg because optimizeLoadInstr() resets it and
|
|
// we need it for markUsesInDebugValueAsUndef().
|
|
unsigned FoldedReg = FoldAsLoadDefReg;
|
|
MachineInstr *DefMI = nullptr;
|
|
MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI,
|
|
FoldAsLoadDefReg,
|
|
DefMI);
|
|
if (FoldMI) {
|
|
// Update LocalMIs since we replaced MI with FoldMI and deleted
|
|
// DefMI.
|
|
DEBUG(dbgs() << "Replacing: " << *MI);
|
|
DEBUG(dbgs() << " With: " << *FoldMI);
|
|
LocalMIs.erase(MI);
|
|
LocalMIs.erase(DefMI);
|
|
LocalMIs.insert(FoldMI);
|
|
MI->eraseFromParent();
|
|
DefMI->eraseFromParent();
|
|
MRI->markUsesInDebugValueAsUndef(FoldedReg);
|
|
FoldAsLoadDefCandidates.erase(FoldedReg);
|
|
++NumLoadFold;
|
|
// MI is replaced with FoldMI.
|
|
Changed = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
bool ValueTracker::getNextSourceFromCopy(unsigned &SrcReg,
|
|
unsigned &SrcSubReg) {
|
|
assert(Def->isCopy() && "Invalid definition");
|
|
// Copy instruction are supposed to be: Def = Src.
|
|
// If someone breaks this assumption, bad things will happen everywhere.
|
|
assert(Def->getNumOperands() == 2 && "Invalid number of operands");
|
|
|
|
if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
|
|
// If we look for a different subreg, it means we want a subreg of src.
|
|
// Bails as we do not support composing subreg yet.
|
|
return false;
|
|
// Otherwise, we want the whole source.
|
|
const MachineOperand &Src = Def->getOperand(1);
|
|
SrcReg = Src.getReg();
|
|
SrcSubReg = Src.getSubReg();
|
|
return true;
|
|
}
|
|
|
|
bool ValueTracker::getNextSourceFromBitcast(unsigned &SrcReg,
|
|
unsigned &SrcSubReg) {
|
|
assert(Def->isBitcast() && "Invalid definition");
|
|
|
|
// Bail if there are effects that a plain copy will not expose.
|
|
if (Def->hasUnmodeledSideEffects())
|
|
return false;
|
|
|
|
// Bitcasts with more than one def are not supported.
|
|
if (Def->getDesc().getNumDefs() != 1)
|
|
return false;
|
|
if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
|
|
// If we look for a different subreg, it means we want a subreg of the src.
|
|
// Bails as we do not support composing subreg yet.
|
|
return false;
|
|
|
|
unsigned SrcIdx = Def->getNumOperands();
|
|
for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
|
|
++OpIdx) {
|
|
const MachineOperand &MO = Def->getOperand(OpIdx);
|
|
if (!MO.isReg() || !MO.getReg())
|
|
continue;
|
|
assert(!MO.isDef() && "We should have skipped all the definitions by now");
|
|
if (SrcIdx != EndOpIdx)
|
|
// Multiple sources?
|
|
return false;
|
|
SrcIdx = OpIdx;
|
|
}
|
|
const MachineOperand &Src = Def->getOperand(SrcIdx);
|
|
SrcReg = Src.getReg();
|
|
SrcSubReg = Src.getSubReg();
|
|
return true;
|
|
}
|
|
|
|
bool ValueTracker::getNextSourceFromRegSequence(unsigned &SrcReg,
|
|
unsigned &SrcSubReg) {
|
|
assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
|
|
"Invalid definition");
|
|
|
|
if (Def->getOperand(DefIdx).getSubReg())
|
|
// If we are composing subreg, bails out.
|
|
// The case we are checking is Def.<subreg> = REG_SEQUENCE.
|
|
// This should almost never happen as the SSA property is tracked at
|
|
// the register level (as opposed to the subreg level).
|
|
// I.e.,
|
|
// Def.sub0 =
|
|
// Def.sub1 =
|
|
// is a valid SSA representation for Def.sub0 and Def.sub1, but not for
|
|
// Def. Thus, it must not be generated.
|
|
// However, some code could theoretically generates a single
|
|
// Def.sub0 (i.e, not defining the other subregs) and we would
|
|
// have this case.
|
|
// If we can ascertain (or force) that this never happens, we could
|
|
// turn that into an assertion.
|
|
return false;
|
|
|
|
if (!TII)
|
|
// We could handle the REG_SEQUENCE here, but we do not want to
|
|
// duplicate the code from the generic TII.
|
|
return false;
|
|
|
|
SmallVector<TargetInstrInfo::RegSubRegPairAndIdx, 8> RegSeqInputRegs;
|
|
if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
|
|
return false;
|
|
|
|
// We are looking at:
|
|
// Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
|
|
// Check if one of the operand defines the subreg we are interested in.
|
|
for (auto &RegSeqInput : RegSeqInputRegs) {
|
|
if (RegSeqInput.SubIdx == DefSubReg) {
|
|
if (RegSeqInput.SubReg)
|
|
// Bails if we have to compose sub registers.
|
|
return false;
|
|
|
|
SrcReg = RegSeqInput.Reg;
|
|
SrcSubReg = RegSeqInput.SubReg;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
// If the subreg we are tracking is super-defined by another subreg,
|
|
// we could follow this value. However, this would require to compose
|
|
// the subreg and we do not do that for now.
|
|
return false;
|
|
}
|
|
|
|
bool ValueTracker::getNextSourceFromInsertSubreg(unsigned &SrcReg,
|
|
unsigned &SrcSubReg) {
|
|
assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
|
|
"Invalid definition");
|
|
|
|
if (Def->getOperand(DefIdx).getSubReg())
|
|
// If we are composing subreg, bails out.
|
|
// Same remark as getNextSourceFromRegSequence.
|
|
// I.e., this may be turned into an assert.
|
|
return false;
|
|
|
|
if (!TII)
|
|
// We could handle the REG_SEQUENCE here, but we do not want to
|
|
// duplicate the code from the generic TII.
|
|
return false;
|
|
|
|
TargetInstrInfo::RegSubRegPair BaseReg;
|
|
TargetInstrInfo::RegSubRegPairAndIdx InsertedReg;
|
|
if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
|
|
return false;
|
|
|
|
// We are looking at:
|
|
// Def = INSERT_SUBREG v0, v1, sub1
|
|
// There are two cases:
|
|
// 1. DefSubReg == sub1, get v1.
|
|
// 2. DefSubReg != sub1, the value may be available through v0.
|
|
|
|
// #1 Check if the inserted register matches the required sub index.
|
|
if (InsertedReg.SubIdx == DefSubReg) {
|
|
SrcReg = InsertedReg.Reg;
|
|
SrcSubReg = InsertedReg.SubReg;
|
|
return true;
|
|
}
|
|
// #2 Otherwise, if the sub register we are looking for is not partial
|
|
// defined by the inserted element, we can look through the main
|
|
// register (v0).
|
|
const MachineOperand &MODef = Def->getOperand(DefIdx);
|
|
// If the result register (Def) and the base register (v0) do not
|
|
// have the same register class or if we have to compose
|
|
// subregisters, bails out.
|
|
if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
|
|
BaseReg.SubReg)
|
|
return false;
|
|
|
|
// Get the TRI and check if the inserted sub-register overlaps with the
|
|
// sub-register we are tracking.
|
|
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
|
|
if (!TRI ||
|
|
(TRI->getSubRegIndexLaneMask(DefSubReg) &
|
|
TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0)
|
|
return false;
|
|
// At this point, the value is available in v0 via the same subreg
|
|
// we used for Def.
|
|
SrcReg = BaseReg.Reg;
|
|
SrcSubReg = DefSubReg;
|
|
return true;
|
|
}
|
|
|
|
bool ValueTracker::getNextSourceFromExtractSubreg(unsigned &SrcReg,
|
|
unsigned &SrcSubReg) {
|
|
assert((Def->isExtractSubreg() ||
|
|
Def->isExtractSubregLike()) && "Invalid definition");
|
|
// We are looking at:
|
|
// Def = EXTRACT_SUBREG v0, sub0
|
|
|
|
// Bails if we have to compose sub registers.
|
|
// Indeed, if DefSubReg != 0, we would have to compose it with sub0.
|
|
if (DefSubReg)
|
|
return false;
|
|
|
|
if (!TII)
|
|
// We could handle the EXTRACT_SUBREG here, but we do not want to
|
|
// duplicate the code from the generic TII.
|
|
return false;
|
|
|
|
TargetInstrInfo::RegSubRegPairAndIdx ExtractSubregInputReg;
|
|
if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
|
|
return false;
|
|
|
|
// Bails if we have to compose sub registers.
|
|
// Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
|
|
if (ExtractSubregInputReg.SubReg)
|
|
return false;
|
|
// Otherwise, the value is available in the v0.sub0.
|
|
SrcReg = ExtractSubregInputReg.Reg;
|
|
SrcSubReg = ExtractSubregInputReg.SubIdx;
|
|
return true;
|
|
}
|
|
|
|
bool ValueTracker::getNextSourceFromSubregToReg(unsigned &SrcReg,
|
|
unsigned &SrcSubReg) {
|
|
assert(Def->isSubregToReg() && "Invalid definition");
|
|
// We are looking at:
|
|
// Def = SUBREG_TO_REG Imm, v0, sub0
|
|
|
|
// Bails if we have to compose sub registers.
|
|
// If DefSubReg != sub0, we would have to check that all the bits
|
|
// we track are included in sub0 and if yes, we would have to
|
|
// determine the right subreg in v0.
|
|
if (DefSubReg != Def->getOperand(3).getImm())
|
|
return false;
|
|
// Bails if we have to compose sub registers.
|
|
// Likewise, if v0.subreg != 0, we would have to compose it with sub0.
|
|
if (Def->getOperand(2).getSubReg())
|
|
return false;
|
|
|
|
SrcReg = Def->getOperand(2).getReg();
|
|
SrcSubReg = Def->getOperand(3).getImm();
|
|
return true;
|
|
}
|
|
|
|
bool ValueTracker::getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg) {
|
|
assert(Def && "This method needs a valid definition");
|
|
|
|
assert(
|
|
(DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) &&
|
|
Def->getOperand(DefIdx).isDef() && "Invalid DefIdx");
|
|
if (Def->isCopy())
|
|
return getNextSourceFromCopy(SrcReg, SrcSubReg);
|
|
if (Def->isBitcast())
|
|
return getNextSourceFromBitcast(SrcReg, SrcSubReg);
|
|
// All the remaining cases involve "complex" instructions.
|
|
// Bails if we did not ask for the advanced tracking.
|
|
if (!UseAdvancedTracking)
|
|
return false;
|
|
if (Def->isRegSequence() || Def->isRegSequenceLike())
|
|
return getNextSourceFromRegSequence(SrcReg, SrcSubReg);
|
|
if (Def->isInsertSubreg() || Def->isInsertSubregLike())
|
|
return getNextSourceFromInsertSubreg(SrcReg, SrcSubReg);
|
|
if (Def->isExtractSubreg() || Def->isExtractSubregLike())
|
|
return getNextSourceFromExtractSubreg(SrcReg, SrcSubReg);
|
|
if (Def->isSubregToReg())
|
|
return getNextSourceFromSubregToReg(SrcReg, SrcSubReg);
|
|
return false;
|
|
}
|
|
|
|
const MachineInstr *ValueTracker::getNextSource(unsigned &SrcReg,
|
|
unsigned &SrcSubReg) {
|
|
// If we reach a point where we cannot move up in the use-def chain,
|
|
// there is nothing we can get.
|
|
if (!Def)
|
|
return nullptr;
|
|
|
|
const MachineInstr *PrevDef = nullptr;
|
|
// Try to find the next source.
|
|
if (getNextSourceImpl(SrcReg, SrcSubReg)) {
|
|
// Update definition, definition index, and subregister for the
|
|
// next call of getNextSource.
|
|
// Update the current register.
|
|
Reg = SrcReg;
|
|
// Update the return value before moving up in the use-def chain.
|
|
PrevDef = Def;
|
|
// If we can still move up in the use-def chain, move to the next
|
|
// defintion.
|
|
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
Def = MRI.getVRegDef(Reg);
|
|
DefIdx = MRI.def_begin(Reg).getOperandNo();
|
|
DefSubReg = SrcSubReg;
|
|
return PrevDef;
|
|
}
|
|
}
|
|
// If we end up here, this means we will not be able to find another source
|
|
// for the next iteration.
|
|
// Make sure any new call to getNextSource bails out early by cutting the
|
|
// use-def chain.
|
|
Def = nullptr;
|
|
return PrevDef;
|
|
}
|