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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
358 lines
13 KiB
C++
358 lines
13 KiB
C++
//===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RABasic function pass, which provides a minimal
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// implementation of the basic register allocator.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "RegAllocBase.h"
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#include "LiveDebugVariables.h"
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#include "LiveRangeEdit.h"
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#include "RenderMachineFunction.h"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Function.h"
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#include "llvm/PassAnalysisSupport.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cstdlib>
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#include <queue>
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using namespace llvm;
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static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
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createBasicRegisterAllocator);
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namespace {
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struct CompSpillWeight {
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bool operator()(LiveInterval *A, LiveInterval *B) const {
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return A->weight < B->weight;
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}
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};
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}
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namespace {
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/// RABasic provides a minimal implementation of the basic register allocation
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/// algorithm. It prioritizes live virtual registers by spill weight and spills
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/// whenever a register is unavailable. This is not practical in production but
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/// provides a useful baseline both for measuring other allocators and comparing
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/// the speed of the basic algorithm against other styles of allocators.
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class RABasic : public MachineFunctionPass, public RegAllocBase
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{
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// context
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MachineFunction *MF;
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// analyses
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LiveStacks *LS;
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RenderMachineFunction *RMF;
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// state
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std::auto_ptr<Spiller> SpillerInstance;
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std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
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CompSpillWeight> Queue;
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// Scratch space. Allocated here to avoid repeated malloc calls in
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// selectOrSplit().
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BitVector UsableRegs;
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public:
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RABasic();
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/// Return the pass name.
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virtual const char* getPassName() const {
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return "Basic Register Allocator";
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}
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/// RABasic analysis usage.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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virtual Spiller &spiller() { return *SpillerInstance; }
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virtual float getPriority(LiveInterval *LI) { return LI->weight; }
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virtual void enqueue(LiveInterval *LI) {
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Queue.push(LI);
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}
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virtual LiveInterval *dequeue() {
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if (Queue.empty())
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return 0;
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LiveInterval *LI = Queue.top();
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Queue.pop();
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return LI;
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}
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virtual unsigned selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs);
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/// Perform register allocation.
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virtual bool runOnMachineFunction(MachineFunction &mf);
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// Helper for spilling all live virtual registers currently unified under preg
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// that interfere with the most recently queried lvr. Return true if spilling
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// was successful, and append any new spilled/split intervals to splitLVRs.
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bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs);
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void spillReg(LiveInterval &VirtReg, unsigned PhysReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs);
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static char ID;
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};
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char RABasic::ID = 0;
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} // end anonymous namespace
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RABasic::RABasic(): MachineFunctionPass(ID) {
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initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
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initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
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initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
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initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
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initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
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initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
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initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
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initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
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}
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void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<AliasAnalysis>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveDebugVariables>();
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AU.addPreserved<LiveDebugVariables>();
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AU.addRequired<CalculateSpillWeights>();
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AU.addRequired<LiveStacks>();
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AU.addPreserved<LiveStacks>();
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AU.addRequiredID(MachineDominatorsID);
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AU.addPreservedID(MachineDominatorsID);
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addRequired<VirtRegMap>();
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AU.addPreserved<VirtRegMap>();
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DEBUG(AU.addRequired<RenderMachineFunction>());
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void RABasic::releaseMemory() {
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SpillerInstance.reset(0);
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RegAllocBase::releaseMemory();
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}
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// Helper for spillInterferences() that spills all interfering vregs currently
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// assigned to this physical register.
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void RABasic::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs) {
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LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
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assert(Q.seenAllInterferences() && "need collectInterferences()");
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const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
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for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
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E = PendingSpills.end(); I != E; ++I) {
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LiveInterval &SpilledVReg = **I;
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DEBUG(dbgs() << "extracting from " <<
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TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
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// Deallocate the interfering vreg by removing it from the union.
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// A LiveInterval instance may not be in a union during modification!
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unassign(SpilledVReg, PhysReg);
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// Spill the extracted interval.
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LiveRangeEdit LRE(SpilledVReg, SplitVRegs);
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spiller().spill(LRE);
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}
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// After extracting segments, the query's results are invalid. But keep the
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// contents valid until we're done accessing pendingSpills.
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Q.clear();
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}
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// Spill or split all live virtual registers currently unified under PhysReg
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// that interfere with VirtReg. The newly spilled or split live intervals are
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// returned by appending them to SplitVRegs.
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bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs) {
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// Record each interference and determine if all are spillable before mutating
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// either the union or live intervals.
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unsigned NumInterferences = 0;
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// Collect interferences assigned to any alias of the physical register.
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for (const uint16_t *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
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LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
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NumInterferences += QAlias.collectInterferingVRegs();
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if (QAlias.seenUnspillableVReg()) {
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return false;
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}
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}
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DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
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" interferences with " << VirtReg << "\n");
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assert(NumInterferences > 0 && "expect interference");
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// Spill each interfering vreg allocated to PhysReg or an alias.
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for (const uint16_t *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
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spillReg(VirtReg, *AliasI, SplitVRegs);
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return true;
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}
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// Driver for the register assignment and splitting heuristics.
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// Manages iteration over the LiveIntervalUnions.
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//
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// This is a minimal implementation of register assignment and splitting that
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// spills whenever we run out of registers.
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//
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// selectOrSplit can only be called once per live virtual register. We then do a
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// single interference test for each register the correct class until we find an
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// available register. So, the number of interference tests in the worst case is
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// |vregs| * |machineregs|. And since the number of interference tests is
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// minimal, there is no value in caching them outside the scope of
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// selectOrSplit().
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unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs) {
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// Check for register mask interference. When live ranges cross calls, the
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// set of usable registers is reduced to the callee-saved ones.
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bool CrossRegMasks = LIS->checkRegMaskInterference(VirtReg, UsableRegs);
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// Populate a list of physical register spill candidates.
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SmallVector<unsigned, 8> PhysRegSpillCands;
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// Check for an available register in this class.
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ArrayRef<unsigned> Order =
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RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
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for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E;
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++I) {
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unsigned PhysReg = *I;
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// If PhysReg is clobbered by a register mask, it isn't useful for
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// allocation or spilling.
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if (CrossRegMasks && !UsableRegs.test(PhysReg))
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continue;
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// Check interference and as a side effect, intialize queries for this
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// VirtReg and its aliases.
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unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
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if (interfReg == 0) {
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// Found an available register.
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return PhysReg;
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}
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LiveIntervalUnion::Query &IntfQ = query(VirtReg, interfReg);
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IntfQ.collectInterferingVRegs(1);
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LiveInterval *interferingVirtReg = IntfQ.interferingVRegs().front();
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// The current VirtReg must either be spillable, or one of its interferences
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// must have less spill weight.
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if (interferingVirtReg->weight < VirtReg.weight ) {
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PhysRegSpillCands.push_back(PhysReg);
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}
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}
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// Try to spill another interfering reg with less spill weight.
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for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
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PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
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if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
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assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
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"Interference after spill.");
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// Tell the caller to allocate to this newly freed physical register.
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return *PhysRegI;
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}
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// No other spill candidates were found, so spill the current VirtReg.
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DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
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if (!VirtReg.isSpillable())
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return ~0u;
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LiveRangeEdit LRE(VirtReg, SplitVRegs);
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spiller().spill(LRE);
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// The live virtual register requesting allocation was spilled, so tell
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// the caller not to allocate anything during this round.
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return 0;
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}
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bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
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<< "********** Function: "
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<< ((Value*)mf.getFunction())->getName() << '\n');
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MF = &mf;
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DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
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RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
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SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
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allocatePhysRegs();
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addMBBLiveIns(MF);
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// Diagnostic output before rewriting
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DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
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// optional HTML output
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DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
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// FIXME: Verification currently must run before VirtRegRewriter. We should
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// make the rewriter a separate pass and override verifyAnalysis instead. When
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// that happens, verification naturally falls under VerifyMachineCode.
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#ifndef NDEBUG
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if (VerifyEnabled) {
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// Verify accuracy of LiveIntervals. The standard machine code verifier
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// ensures that each LiveIntervals covers all uses of the virtual reg.
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// FIXME: MachineVerifier is badly broken when using the standard
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// spiller. Always use -spiller=inline with -verify-regalloc. Even with the
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// inline spiller, some tests fail to verify because the coalescer does not
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// always generate verifiable code.
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MF->verify(this, "In RABasic::verify");
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// Verify that LiveIntervals are partitioned into unions and disjoint within
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// the unions.
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verify();
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}
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#endif // !NDEBUG
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// Run rewriter
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VRM->rewrite(LIS->getSlotIndexes());
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// Write out new DBG_VALUE instructions.
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getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
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// All machine operands and other references to virtual registers have been
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// replaced. Remove the virtual registers and release all the transient data.
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VRM->clearAllVirt();
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MRI->clearVirtRegs();
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releaseMemory();
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return true;
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}
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FunctionPass* llvm::createBasicRegisterAllocator()
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{
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return new RABasic();
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}
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