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https://github.com/c64scene-ar/llvm-6502.git
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c9aa7dfee4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2035 91177308-0d34-0410-b5e6-96231b3b80d8
623 lines
22 KiB
C++
623 lines
22 KiB
C++
// $Id$ -*- C++ -*--
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//***************************************************************************
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// File:
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// SparcInternals.h
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//
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// Purpose:
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// This file defines stuff that is to be private to the Sparc
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// backend, but is shared among different portions of the backend.
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//**************************************************************************/
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#ifndef SPARC_INTERNALS_H
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#define SPARC_INTERNALS_H
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Target/MachineSchedInfo.h"
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#include "llvm/Target/MachineFrameInfo.h"
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#include "llvm/Target/MachineCacheInfo.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/Type.h"
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#include <sys/types.h>
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class LiveRange;
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class UltraSparc;
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class PhyRegAlloc;
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// OpCodeMask definitions for the Sparc V9
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//
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const OpCodeMask Immed = 0x00002000; // immed or reg operand?
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const OpCodeMask Annul = 0x20000000; // annul delay instr?
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const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
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enum SparcInstrSchedClass {
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SPARC_NONE, /* Instructions with no scheduling restrictions */
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SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
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SPARC_IEU0, /* Integer class IEU0 */
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SPARC_IEU1, /* Integer class IEU1 */
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SPARC_FPM, /* FP Multiply or Divide instructions */
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SPARC_FPA, /* All other FP instructions */
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SPARC_CTI, /* Control-transfer instructions */
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SPARC_LD, /* Load instructions */
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SPARC_ST, /* Store instructions */
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SPARC_SINGLE, /* Instructions that must issue by themselves */
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SPARC_INV, /* This should stay at the end for the next value */
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SPARC_NUM_SCHED_CLASSES = SPARC_INV
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};
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//---------------------------------------------------------------------------
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// enum SparcMachineOpCode.
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// const MachineInstrDescriptor SparcMachineInstrDesc[]
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//
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// Purpose:
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// Description of UltraSparc machine instructions.
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//
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//---------------------------------------------------------------------------
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enum SparcMachineOpCode {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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ENUM,
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#include "SparcInstr.def"
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// End-of-array marker
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INVALID_OPCODE,
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NUM_REAL_OPCODES = PHI, // number of valid opcodes
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NUM_TOTAL_OPCODES = INVALID_OPCODE
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};
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// Array of machine instruction descriptions...
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extern const MachineInstrDescriptor SparcMachineInstrDesc[];
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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//
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// Purpose:
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// Information about individual instructions.
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// Most information is stored in the SparcMachineInstrDesc array above.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class MachineInstrInfo.
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//---------------------------------------------------------------------------
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class UltraSparcInstrInfo : public MachineInstrInfo {
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public:
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/*ctor*/ UltraSparcInstrInfo(const TargetMachine& tgt);
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//
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// All immediate constants are in position 1 except the
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// store instructions.
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//
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virtual int getImmedConstantPos(MachineOpCode opCode) const {
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bool ignore;
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if (this->maxImmedConstant(opCode, ignore) != 0)
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{
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assert(! this->isStore((MachineOpCode) STB - 1)); // first store is STB
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assert(! this->isStore((MachineOpCode) STD + 1)); // last store is STD
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return (opCode >= STB && opCode <= STD)? 2 : 1;
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}
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else
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return -1;
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}
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virtual bool hasResultInterlock (MachineOpCode opCode) const
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{
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// All UltraSPARC instructions have interlocks (note that delay slots
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// are not considered here).
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// However, instructions that use the result of an FCMP produce a
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// 9-cycle stall if they are issued less than 3 cycles after the FCMP.
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// Force the compiler to insert a software interlock (i.e., gap of
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// 2 other groups, including NOPs if necessary).
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return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
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}
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//-------------------------------------------------------------------------
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. The generated instructions are
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// returned in `minstrVec'. Any temporary registers (TmpInstruction)
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// created are returned in `tempVec'.
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//
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virtual void CreateCodeToLoadConst(Method* method,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& minstrVec,
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std::vector<TmpInstruction*>& tmp) const;
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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// val must be an integral type. dest must be a Float or Double.
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// The generated instructions are returned in `minstrVec'.
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// Any temp. registers (TmpInstruction) created are returned in `tempVec'.
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//
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virtual void CreateCodeToCopyIntToFloat(Method* method,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& minstr,
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std::vector<TmpInstruction*>& temp,
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TargetMachine& target) const;
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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// See the previous function for information about return values.
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//
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virtual void CreateCodeToCopyFloatToInt(Method* method,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& minstr,
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std::vector<TmpInstruction*>& temp,
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TargetMachine& target) const;
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// create copy instruction(s)
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virtual void CreateCopyInstructionsByType(const TargetMachine& target,
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Method* method,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& minstr) const;
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};
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//----------------------------------------------------------------------------
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// class UltraSparcRegInfo
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//
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// This class implements the virtual class MachineRegInfo for Sparc.
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//
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//----------------------------------------------------------------------------
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class UltraSparcRegInfo : public MachineRegInfo {
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// The actual register classes in the Sparc
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//
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enum RegClassIDs {
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IntRegClassID, // Integer
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FloatRegClassID, // Float (both single/double)
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IntCCRegClassID, // Int Condition Code
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FloatCCRegClassID // Float Condition code
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};
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// Type of registers available in Sparc. There can be several reg types
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// in the same class. For instace, the float reg class has Single/Double
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// types
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//
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enum RegTypes {
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IntRegType,
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FPSingleRegType,
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FPDoubleRegType,
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IntCCRegType,
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FloatCCRegType
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};
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// **** WARNING: If the above enum order is changed, also modify
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// getRegisterClassOfValue method below since it assumes this particular
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// order for efficiency.
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// reverse pointer to get info about the ultra sparc machine
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//
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const UltraSparc *const UltraSparcInfo;
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// Number of registers used for passing int args (usually 6: %o0 - %o5)
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//
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unsigned const NumOfIntArgRegs;
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// Number of registers used for passing float args (usually 32: %f0 - %f31)
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//
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unsigned const NumOfFloatArgRegs;
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// An out of bound register number that can be used to initialize register
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// numbers. Useful for error detection.
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//
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int const InvalidRegNum;
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// ======================== Private Methods =============================
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// The following methods are used to color special live ranges (e.g.
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// method args and return values etc.) with specific hardware registers
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// as required. See SparcRegInfo.cpp for the implementation.
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//
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void setCallOrRetArgCol(LiveRange *LR, unsigned RegNo,
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const MachineInstr *MI,
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std::hash_map<const MachineInstr *,
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AddedInstrns *> &AIMap) const;
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MachineInstr *getCopy2RegMI(const Value *SrcVal, unsigned Reg,
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unsigned RegClassID) const;
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void suggestReg4RetAddr(const MachineInstr *RetMI,
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LiveRangeInfo &LRI) const;
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void suggestReg4CallAddr(const MachineInstr *CallMI, LiveRangeInfo &LRI,
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std::vector<RegClass *> RCList) const;
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// The following methods are used to find the addresses etc. contained
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// in specail machine instructions like CALL/RET
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//
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Value *getValue4ReturnAddr(const MachineInstr *MInst) const;
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const Value *getCallInstRetAddr(const MachineInstr *CallMI) const;
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unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
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// The following 3 methods are used to find the RegType (see enum above)
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// of a LiveRange, Value and using the unified RegClassID
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int getRegType(const LiveRange *LR) const;
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int getRegType(const Value *Val) const;
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int getRegType(int reg) const;
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// The following methods are used to generate copy instructions to move
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// data between condition code registers
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//
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MachineInstr *cpCCR2IntMI(unsigned IntReg) const;
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MachineInstr *cpInt2CCRMI(unsigned IntReg) const;
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// Used to generate a copy instruction based on the register class of
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// value.
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//
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MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
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int RegType) const;
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// The following 2 methods are used to order the instructions addeed by
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// the register allocator in association with method calling. See
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// SparcRegInfo.cpp for more details
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//
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void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
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MachineInstr *UnordInst,
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PhyRegAlloc &PRA) const;
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void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
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std::vector<MachineInstr *> &OrdVec,
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PhyRegAlloc &PRA) const;
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// To find whether a particular call is to a var arg method
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//
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bool isVarArgCall(const MachineInstr *CallMI) const;
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public:
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UltraSparcRegInfo(const UltraSparc &tgt);
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// To get complete machine information structure using the machine register
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// information
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//
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inline const UltraSparc &getUltraSparcInfo() const {
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return *UltraSparcInfo;
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}
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// To find the register class used for a specified Type
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//
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inline unsigned getRegClassIDOfType(const Type *type,
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bool isCCReg = false) const {
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Type::PrimitiveID ty = type->getPrimitiveID();
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unsigned res;
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// FIXME: Comparing types like this isn't very safe...
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if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
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(ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
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res = IntRegClassID; // sparc int reg (ty=0: void)
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else if (ty <= Type::DoubleTyID)
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res = FloatRegClassID; // sparc float reg class
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else {
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//std::cerr << "TypeID: " << ty << "\n";
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assert(0 && "Cannot resolve register class for type");
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return 0;
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}
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if(isCCReg)
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return res + 2; // corresponidng condition code regiser
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else
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return res;
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}
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// To find the register class of a Value
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//
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inline unsigned getRegClassIDOfValue(const Value *Val,
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bool isCCReg = false) const {
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return getRegClassIDOfType(Val->getType(), isCCReg);
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}
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// getZeroRegNum - returns the register that contains always zero this is the
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// unified register number
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//
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virtual int getZeroRegNum() const;
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// getCallAddressReg - returns the reg used for pushing the address when a
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// method is called. This can be used for other purposes between calls
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//
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unsigned getCallAddressReg() const;
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// Returns the register containing the return address.
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// It should be made sure that this register contains the return
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// value when a return instruction is reached.
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//
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unsigned getReturnAddressReg() const;
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// The following methods are used to color special live ranges (e.g.
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// method args and return values etc.) with specific hardware registers
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// as required. See SparcRegInfo.cpp for the implementation for Sparc.
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//
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void suggestRegs4MethodArgs(const Method *Meth,
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LiveRangeInfo& LRI) const;
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void suggestRegs4CallArgs(const MachineInstr *CallMI,
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LiveRangeInfo& LRI,
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std::vector<RegClass *> RCL) const;
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void suggestReg4RetValue(const MachineInstr *RetMI,
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LiveRangeInfo& LRI) const;
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void colorMethodArgs(const Method *Meth, LiveRangeInfo &LRI,
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AddedInstrns *FirstAI) const;
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void colorCallArgs(const MachineInstr *CallMI, LiveRangeInfo &LRI,
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AddedInstrns *CallAI, PhyRegAlloc &PRA,
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const BasicBlock *BB) const;
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void colorRetValue(const MachineInstr *RetI, LiveRangeInfo& LRI,
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AddedInstrns *RetAI) const;
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// method used for printing a register for debugging purposes
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//
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static void printReg(const LiveRange *LR);
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// this method provides a unique number for each register
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//
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inline int getUnifiedRegNum(int RegClassID, int reg) const {
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if( RegClassID == IntRegClassID && reg < 32 )
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return reg;
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else if ( RegClassID == FloatRegClassID && reg < 64)
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return reg + 32; // we have 32 int regs
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else if( RegClassID == FloatCCRegClassID && reg < 4)
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return reg + 32 + 64; // 32 int, 64 float
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else if( RegClassID == IntCCRegClassID )
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return reg + 4+ 32 + 64; // only int cc reg
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else if (reg==InvalidRegNum)
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return InvalidRegNum;
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else
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assert(0 && "Invalid register class or reg number");
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return 0;
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}
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// given the unified register number, this gives the name
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// for generating assembly code or debugging.
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//
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virtual const std::string getUnifiedRegName(int reg) const;
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// returns the # of bytes of stack space allocated for each register
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// type. For Sparc, currently we allocate 8 bytes on stack for all
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// register types. We can optimize this later if necessary to save stack
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// space (However, should make sure that stack alignment is correct)
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//
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inline int getSpilledRegSize(int RegType) const {
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return 8;
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}
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// To obtain the return value contained in a CALL machine instruction
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//
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const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
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// The following methods are used to generate "copy" machine instructions
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// for an architecture.
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//
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MachineInstr * cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
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int RegType) const;
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MachineInstr * cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
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int Offset, int RegType) const;
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MachineInstr * cpMem2RegMI(unsigned SrcPtrReg, int Offset,
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unsigned DestReg, int RegType) const;
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MachineInstr* cpValue2Value(Value *Src, Value *Dest) const;
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// To see whether a register is a volatile (i.e., whehter it must be
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// preserved acorss calls)
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//
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inline bool isRegVolatile(int RegClassID, int Reg) const {
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return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
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}
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virtual unsigned getFramePointer() const;
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virtual unsigned getStackPointer() const;
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virtual int getInvalidRegNum() const {
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return InvalidRegNum;
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}
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// This method inserts the caller saving code for call instructions
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//
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void insertCallerSavingCode(const MachineInstr *MInst,
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const BasicBlock *BB, PhyRegAlloc &PRA ) const;
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};
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//---------------------------------------------------------------------------
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// class UltraSparcSchedInfo
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//
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// Purpose:
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// Interface to instruction scheduling information for UltraSPARC.
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// The parameter values above are based on UltraSPARC IIi.
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//---------------------------------------------------------------------------
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class UltraSparcSchedInfo: public MachineSchedInfo {
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public:
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UltraSparcSchedInfo(const TargetMachine &tgt);
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protected:
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virtual void initializeResources();
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};
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//---------------------------------------------------------------------------
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// class UltraSparcFrameInfo
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//
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// Purpose:
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// Interface to stack frame layout info for the UltraSPARC.
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// Starting offsets for each area of the stack frame are aligned at
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// a multiple of getStackFrameSizeAlignment().
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//---------------------------------------------------------------------------
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class UltraSparcFrameInfo: public MachineFrameInfo {
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public:
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UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
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public:
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int getStackFrameSizeAlignment () const { return StackFrameSizeAlignment;}
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int getMinStackFrameSize () const { return MinStackFrameSize; }
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int getNumFixedOutgoingArgs () const { return NumFixedOutgoingArgs; }
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int getSizeOfEachArgOnStack () const { return SizeOfEachArgOnStack; }
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bool argsOnStackHaveFixedSize () const { return true; }
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//
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// These methods compute offsets using the frame contents for a
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// particular method. The frame contents are obtained from the
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// MachineCodeInfoForMethod object for the given method.
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//
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int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
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bool& pos) const
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{
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pos = true; // arguments area grows upwards
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return FirstIncomingArgOffsetFromFP;
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}
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int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
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bool& pos) const
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{
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pos = true; // arguments area grows upwards
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return FirstOutgoingArgOffsetFromSP;
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}
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int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
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bool& pos)const
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{
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pos = true; // arguments area grows upwards
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return FirstOptionalOutgoingArgOffsetFromSP;
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}
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int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
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bool& pos) const;
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int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
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bool& pos) const;
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int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
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bool& pos) const;
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int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
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bool& pos) const;
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//
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// These methods specify the base register used for each stack area
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// (generally FP or SP)
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//
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virtual int getIncomingArgBaseRegNum() const {
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return (int) target.getRegInfo().getFramePointer();
|
|
}
|
|
virtual int getOutgoingArgBaseRegNum() const {
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
}
|
|
virtual int getOptionalOutgoingArgBaseRegNum() const {
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
}
|
|
virtual int getAutomaticVarBaseRegNum() const {
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
}
|
|
virtual int getRegSpillAreaBaseRegNum() const {
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
}
|
|
virtual int getDynamicAreaBaseRegNum() const {
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
}
|
|
|
|
private:
|
|
// All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
|
|
static const int OFFSET = (int) 0x7ff;
|
|
static const int StackFrameSizeAlignment = 16;
|
|
static const int MinStackFrameSize = 176;
|
|
static const int NumFixedOutgoingArgs = 6;
|
|
static const int SizeOfEachArgOnStack = 8;
|
|
static const int StaticAreaOffsetFromFP = 0 + OFFSET;
|
|
static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
|
|
static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
|
|
static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
|
|
static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
|
|
};
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class UltraSparcCacheInfo
|
|
//
|
|
// Purpose:
|
|
// Interface to cache parameters for the UltraSPARC.
|
|
// Just use defaults for now.
|
|
//---------------------------------------------------------------------------
|
|
|
|
class UltraSparcCacheInfo: public MachineCacheInfo {
|
|
public:
|
|
UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
|
|
};
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class UltraSparcMachine
|
|
//
|
|
// Purpose:
|
|
// Primary interface to machine description for the UltraSPARC.
|
|
// Primarily just initializes machine-dependent parameters in
|
|
// class TargetMachine, and creates machine-dependent subclasses
|
|
// for classes such as InstrInfo, SchedInfo and RegInfo.
|
|
//---------------------------------------------------------------------------
|
|
|
|
class UltraSparc : public TargetMachine {
|
|
private:
|
|
UltraSparcInstrInfo instrInfo;
|
|
UltraSparcSchedInfo schedInfo;
|
|
UltraSparcRegInfo regInfo;
|
|
UltraSparcFrameInfo frameInfo;
|
|
UltraSparcCacheInfo cacheInfo;
|
|
public:
|
|
UltraSparc();
|
|
|
|
virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
|
|
virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
|
|
virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
|
|
virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
|
|
virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
|
|
|
|
//
|
|
// addPassesToEmitAssembly - Add passes to the specified pass manager to get
|
|
// assembly langage code emited. For sparc, we have to do ...
|
|
//
|
|
virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
|
|
|
|
private:
|
|
Pass *getMethodAsmPrinterPass(PassManager &PM, std::ostream &Out);
|
|
Pass *getModuleAsmPrinterPass(PassManager &PM, std::ostream &Out);
|
|
Pass *getEmitBytecodeToAsmPass(std::ostream &Out);
|
|
};
|
|
|
|
#endif
|