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It is OK for an alias live range to overlap if there is a copy to or from the physical register. CoalescerPair can work out if the copy is coalescable independently of the alias. This means that we can join with the actual destination interval instead of using the getOrigDstReg() hack. It is no longer necessary to merge clobber ranges into subregisters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107695 91177308-0d34-0410-b5e6-96231b3b80d8
203 lines
6.6 KiB
C++
203 lines
6.6 KiB
C++
//===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the generic RegisterCoalescer interface which
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// is used as the common interface used by all clients and
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// implementations of register coalescing.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Pass.h"
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using namespace llvm;
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// Register the RegisterCoalescer interface, providing a nice name to refer to.
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static RegisterAnalysisGroup<RegisterCoalescer> Z("Register Coalescer");
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char RegisterCoalescer::ID = 0;
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// RegisterCoalescer destructor: DO NOT move this to the header file
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// for RegisterCoalescer or else clients of the RegisterCoalescer
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// class may not depend on the RegisterCoalescer.o file in the current
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// .a file, causing alias analysis support to not be included in the
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// tool correctly!
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//
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RegisterCoalescer::~RegisterCoalescer() {}
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unsigned CoalescerPair::compose(unsigned a, unsigned b) const {
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if (!a) return b;
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if (!b) return a;
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return tri_.composeSubRegIndices(a, b);
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}
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bool CoalescerPair::isMoveInstr(const MachineInstr *MI,
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unsigned &Src, unsigned &Dst,
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unsigned &SrcSub, unsigned &DstSub) const {
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if (MI->isCopy()) {
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Dst = MI->getOperand(0).getReg();
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DstSub = MI->getOperand(0).getSubReg();
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Src = MI->getOperand(1).getReg();
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SrcSub = MI->getOperand(1).getSubReg();
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} else if (MI->isExtractSubreg()) {
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Dst = MI->getOperand(0).getReg();
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DstSub = MI->getOperand(0).getSubReg();
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Src = MI->getOperand(1).getReg();
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SrcSub = compose(MI->getOperand(1).getSubReg(), MI->getOperand(2).getImm());
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} else if (MI->isInsertSubreg() || MI->isSubregToReg()) {
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Dst = MI->getOperand(0).getReg();
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DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());
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Src = MI->getOperand(2).getReg();
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SrcSub = MI->getOperand(2).getSubReg();
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} else if (!tii_.isMoveInstr(*MI, Src, Dst, SrcSub, DstSub)) {
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return false;
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}
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return true;
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}
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bool CoalescerPair::setRegisters(const MachineInstr *MI) {
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srcReg_ = dstReg_ = subIdx_ = 0;
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newRC_ = 0;
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flipped_ = crossClass_ = false;
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unsigned Src, Dst, SrcSub, DstSub;
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if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub))
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return false;
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partial_ = SrcSub || DstSub;
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// If one register is a physreg, it must be Dst.
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if (TargetRegisterInfo::isPhysicalRegister(Src)) {
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if (TargetRegisterInfo::isPhysicalRegister(Dst))
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return false;
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std::swap(Src, Dst);
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std::swap(SrcSub, DstSub);
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flipped_ = true;
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}
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const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
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// Eliminate DstSub on a physreg.
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if (DstSub) {
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Dst = tri_.getSubReg(Dst, DstSub);
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if (!Dst) return false;
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DstSub = 0;
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}
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// Eliminate SrcSub by picking a corresponding Dst superregister.
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if (SrcSub) {
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Dst = tri_.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
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if (!Dst) return false;
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SrcSub = 0;
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} else if (!MRI.getRegClass(Src)->contains(Dst)) {
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return false;
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}
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} else {
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// Both registers are virtual.
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// Both registers have subreg indices.
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if (SrcSub && DstSub) {
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// For now we only handle the case of identical indices in commensurate
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// registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg
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// FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg.
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if (SrcSub != DstSub)
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return false;
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const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
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const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
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if (!getCommonSubClass(DstRC, SrcRC))
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return false;
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SrcSub = DstSub = 0;
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}
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// There can be no SrcSub.
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if (SrcSub) {
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std::swap(Src, Dst);
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DstSub = SrcSub;
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SrcSub = 0;
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assert(!flipped_ && "Unexpected flip");
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flipped_ = true;
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}
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// Find the new register class.
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const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
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const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
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if (DstSub)
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newRC_ = tri_.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
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else
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newRC_ = getCommonSubClass(DstRC, SrcRC);
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if (!newRC_)
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return false;
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crossClass_ = newRC_ != DstRC || newRC_ != SrcRC;
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}
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// Check our invariants
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assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
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assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
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"Cannot have a physical SubIdx");
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srcReg_ = Src;
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dstReg_ = Dst;
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subIdx_ = DstSub;
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return true;
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}
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bool CoalescerPair::flip() {
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if (subIdx_ || TargetRegisterInfo::isPhysicalRegister(dstReg_))
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return false;
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std::swap(srcReg_, dstReg_);
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flipped_ = !flipped_;
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return true;
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}
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bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
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if (!MI)
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return false;
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unsigned Src, Dst, SrcSub, DstSub;
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if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub))
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return false;
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// Find the virtual register that is srcReg_.
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if (Dst == srcReg_) {
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std::swap(Src, Dst);
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std::swap(SrcSub, DstSub);
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} else if (Src != srcReg_) {
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return false;
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}
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// Now check that Dst matches dstReg_.
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if (TargetRegisterInfo::isPhysicalRegister(dstReg_)) {
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if (!TargetRegisterInfo::isPhysicalRegister(Dst))
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return false;
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assert(!subIdx_ && "Inconsistent CoalescerPair state.");
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// DstSub could be set for a physreg from INSERT_SUBREG.
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if (DstSub)
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Dst = tri_.getSubReg(Dst, DstSub);
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// Full copy of Src.
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if (!SrcSub)
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return dstReg_ == Dst;
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// This is a partial register copy. Check that the parts match.
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return tri_.getSubReg(dstReg_, SrcSub) == Dst;
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} else {
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// dstReg_ is virtual.
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if (dstReg_ != Dst)
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return false;
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// Registers match, do the subregisters line up?
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return compose(subIdx_, SrcSub) == DstSub;
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}
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}
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// Because of the way .a files work, we must force the SimpleRC
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// implementation to be pulled in if the RegisterCoalescer classes are
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// pulled in. Otherwise we run the risk of RegisterCoalescer being
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// used, but the default implementation not being linked into the tool
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// that uses it.
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DEFINING_FILE_FOR(RegisterCoalescer)
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