mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 04:29:44 +00:00
70933266ae
tweaking when we start using it for object file emission or JIT, but it's a start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
434 lines
14 KiB
C++
434 lines
14 KiB
C++
//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARMMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-emitter"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMFixupKinds.h"
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#include "ARMInstrInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
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STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
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namespace {
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class ARMMCCodeEmitter : public MCCodeEmitter {
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ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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MCContext &Ctx;
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public:
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ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
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: TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
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}
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~ARMMCCodeEmitter() {}
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unsigned getNumFixupKinds() const { return 2; }
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[] = {
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{ "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
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};
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if (Kind < FirstTargetFixupKind)
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return MCCodeEmitter::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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unsigned getMachineSoImmOpValue(unsigned SoImm) const;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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unsigned getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
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unsigned &Reg, unsigned &Imm,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
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/// operand.
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uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
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uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getCCOutOpValue - Return encoding of the 's' bit.
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unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
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// '1' respectively.
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return MI.getOperand(Op).getReg() == ARM::CPSR;
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}
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/// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
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unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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unsigned SoImm = MI.getOperand(Op).getImm();
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int SoImmVal = ARM_AM::getSOImmVal(SoImm);
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assert(SoImmVal != -1 && "Not a valid so_imm value!");
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// Encode rotate_imm.
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unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
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<< ARMII::SoRotImmShift;
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// Encode immed_8.
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Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
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return Binary;
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}
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/// getSORegOpValue - Return an encoded so_reg shifted register value.
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unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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switch (MI.getOperand(Op).getImm()) {
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default: assert (0 && "Not a valid rot_imm value!");
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case 0: return 0;
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case 8: return 1;
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case 16: return 2;
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case 24: return 3;
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}
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}
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unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return MI.getOperand(Op).getImm() - 1;
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}
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unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 64 - MI.getOperand(Op).getImm();
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}
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unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EmitByte(unsigned char C, raw_ostream &OS) const {
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OS << (char)C;
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}
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void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
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// Output the constant in little endian byte order.
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for (unsigned i = 0; i != Size; ++i) {
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EmitByte(Val & 255, OS);
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Val >>= 8;
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}
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}
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
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MCContext &Ctx) {
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return new ARMMCCodeEmitter(TM, Ctx);
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned ARMMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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unsigned Reg = MO.getReg();
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unsigned RegNo = getARMRegisterNumbering(Reg);
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// Q registers are encodes as 2x their register number.
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switch (Reg) {
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default:
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return RegNo;
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case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
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case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
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case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
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case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
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return 2 * RegNo;
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}
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} else if (MO.isImm()) {
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return static_cast<unsigned>(MO.getImm());
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} else if (MO.isFPImm()) {
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return static_cast<unsigned>(APFloat(MO.getFPImm())
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.bitcastToAPInt().getHiBits(32).getLimitedValue());
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}
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#ifndef NDEBUG
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errs() << MO;
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#endif
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llvm_unreachable(0);
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return 0;
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}
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/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
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bool ARMMCCodeEmitter::
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EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
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unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
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Reg = getARMRegisterNumbering(MO.getReg());
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int32_t SImm = MO1.getImm();
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bool isAdd = true;
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// Special value for #-0
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if (SImm == INT32_MIN)
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SImm = 0;
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// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
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if (SImm < 0) {
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SImm = -SImm;
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isAdd = false;
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}
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Imm = SImm;
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return isAdd;
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}
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/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
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uint32_t ARMMCCodeEmitter::
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getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// {17-13} = reg
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// {12} = (U)nsigned (add == '1', sub == '0')
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// {11-0} = imm12
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unsigned Reg, Imm12;
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bool isAdd = true;
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// If The first operand isn't a register, we have a label reference.
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const MCOperand &MO = MI.getOperand(OpIdx);
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if (!MO.isReg()) {
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Reg = ARM::PC; // Rn is PC.
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Imm12 = 0;
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assert(MO.isExpr() && "Unexpected machine operand type!");
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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++MCNumCPRelocations;
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} else
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isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
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if (Reg == ARM::PC)
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return ARM::PC << 13; // Rn is PC;
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uint32_t Binary = Imm12 & 0xfff;
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// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
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if (isAdd)
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Binary |= (1 << 12);
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Binary |= (Reg << 13);
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return Binary;
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}
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/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
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uint32_t ARMMCCodeEmitter::
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getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// {12-9} = reg
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// {8} = (U)nsigned (add == '1', sub == '0')
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// {7-0} = imm8
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unsigned Reg, Imm8;
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// If The first operand isn't a register, we have a label reference.
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const MCOperand &MO = MI.getOperand(OpIdx);
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if (!MO.isReg()) {
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Reg = ARM::PC; // Rn is PC.
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Imm8 = 0;
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assert(MO.isExpr() && "Unexpected machine operand type!");
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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++MCNumCPRelocations;
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} else
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EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
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if (Reg == ARM::PC)
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return ARM::PC << 9; // Rn is PC;
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uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
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// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
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if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
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Binary |= (1 << 8);
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Binary |= (Reg << 9);
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return Binary;
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}
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unsigned ARMMCCodeEmitter::
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getSORegOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
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// shifted. The second is either Rs, the amount to shift by, or reg0 in which
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// case the imm contains the amount to shift by.
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//
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// {3-0} = Rm.
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// {4} = 1 if reg shift, 0 if imm shift
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// {6-5} = type
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// If reg shift:
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// {11-8} = Rs
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// {7} = 0
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// else (imm shift)
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// {11-7} = imm
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const MCOperand &MO = MI.getOperand(OpIdx);
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const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
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const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
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ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
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// Encode Rm.
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unsigned Binary = getARMRegisterNumbering(MO.getReg());
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// Encode the shift opcode.
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unsigned SBits = 0;
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unsigned Rs = MO1.getReg();
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if (Rs) {
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// Set shift operand (bit[7:4]).
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// LSL - 0001
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// LSR - 0011
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// ASR - 0101
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// ROR - 0111
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// RRX - 0110 and bit[11:8] clear.
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switch (SOpc) {
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default: llvm_unreachable("Unknown shift opc!");
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case ARM_AM::lsl: SBits = 0x1; break;
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case ARM_AM::lsr: SBits = 0x3; break;
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case ARM_AM::asr: SBits = 0x5; break;
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case ARM_AM::ror: SBits = 0x7; break;
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case ARM_AM::rrx: SBits = 0x6; break;
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}
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} else {
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// Set shift operand (bit[6:4]).
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// LSL - 000
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// LSR - 010
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// ASR - 100
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// ROR - 110
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switch (SOpc) {
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default: llvm_unreachable("Unknown shift opc!");
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case ARM_AM::lsl: SBits = 0x0; break;
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case ARM_AM::lsr: SBits = 0x2; break;
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case ARM_AM::asr: SBits = 0x4; break;
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case ARM_AM::ror: SBits = 0x6; break;
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}
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}
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Binary |= SBits << 4;
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if (SOpc == ARM_AM::rrx)
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return Binary;
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// Encode the shift operation Rs or shift_imm (except rrx).
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if (Rs) {
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// Encode Rs bit[11:8].
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assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
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return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
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}
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// Encode shift_imm bit[11:7].
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return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
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}
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unsigned ARMMCCodeEmitter::
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getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
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// msb of the mask.
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const MCOperand &MO = MI.getOperand(Op);
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uint32_t v = ~MO.getImm();
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uint32_t lsb = CountTrailingZeros_32(v);
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uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
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assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
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return lsb | (msb << 5);
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}
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unsigned ARMMCCodeEmitter::
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getRegisterListOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
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// register in the list, set the corresponding bit.
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unsigned Binary = 0;
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for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
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unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
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Binary |= 1 << regno;
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}
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return Binary;
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}
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unsigned ARMMCCodeEmitter::
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getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &Reg = MI.getOperand(Op);
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const MCOperand &Imm = MI.getOperand(Op + 1);
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unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
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unsigned Align = 0;
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switch (Imm.getImm()) {
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default: break;
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case 2:
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case 4:
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case 8: Align = 0x01; break;
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case 16: Align = 0x02; break;
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case 32: Align = 0x03; break;
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}
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return RegNo | (Align << 4);
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}
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unsigned ARMMCCodeEmitter::
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getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(Op);
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if (MO.getReg() == 0) return 0x0D;
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return MO.getReg();
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}
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void ARMMCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Pseudo instructions don't get encoded.
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const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
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if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
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return;
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EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, OS);
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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#include "ARMGenMCCodeEmitter.inc"
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