mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-05 13:29:22 +00:00
c7b902e7fe
The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. This patch has been updated to address Nadav's review comments - Optimize only at >= O1 and don't do optimization if -Os is set - Stores MachineBasicBlock* instead of BBNum - Uses DenseMap instead of std::map - Fixes placement of braces Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171879 91177308-0d34-0410-b5e6-96231b3b80d8
360 lines
7.9 KiB
LLVM
360 lines
7.9 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=generic | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=atom | FileCheck -check-prefix=ATOM %s
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; PR5757
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%0 = type { i64, i32 }
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define i32 @test1(%0* %p, %0* %q, i1 %r) nounwind {
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%t0 = load %0* %p
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%t1 = load %0* %q
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%t4 = select i1 %r, %0 %t0, %0 %t1
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%t5 = extractvalue %0 %t4, 1
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ret i32 %t5
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; CHECK: test1:
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; CHECK: cmovneq %rdi, %rsi
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; CHECK: movl (%rsi), %eax
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; ATOM: test1:
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; ATOM: cmovneq %rdi, %rsi
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; ATOM: movl (%rsi), %eax
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}
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; PR2139
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define i32 @test2() nounwind {
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entry:
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%tmp73 = tail call i1 @return_false() ; <i8> [#uses=1]
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%g.0 = select i1 %tmp73, i16 0, i16 -480 ; <i16> [#uses=2]
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%tmp7778 = sext i16 %g.0 to i32 ; <i32> [#uses=1]
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%tmp80 = shl i32 %tmp7778, 3 ; <i32> [#uses=2]
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%tmp87 = icmp sgt i32 %tmp80, 32767 ; <i1> [#uses=1]
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br i1 %tmp87, label %bb90, label %bb91
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bb90: ; preds = %bb84, %bb72
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unreachable
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bb91: ; preds = %bb84
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ret i32 0
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; CHECK: test2:
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; CHECK: movnew
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; CHECK: movswl
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; ATOM: test2:
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; ATOM: movnew
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; ATOM: movswl
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}
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declare i1 @return_false()
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;; Select between two floating point constants.
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define float @test3(i32 %x) nounwind readnone {
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entry:
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%0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
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%iftmp.0.0 = select i1 %0, float 4.200000e+01, float 2.300000e+01 ; <float> [#uses=1]
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ret float %iftmp.0.0
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; CHECK: test3:
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; CHECK: movss {{.*}},4), %xmm0
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; ATOM: test3:
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; ATOM: movss {{.*}},4), %xmm0
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}
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define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly {
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entry:
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%0 = fcmp olt double %F, 4.200000e+01 ; <i1> [#uses=1]
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%iftmp.0.0 = select i1 %0, i32 4, i32 0 ; <i32> [#uses=1]
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%1 = getelementptr i8* %P, i32 %iftmp.0.0 ; <i8*> [#uses=1]
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%2 = load i8* %1, align 1 ; <i8> [#uses=1]
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ret i8 %2
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; CHECK: test4:
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; CHECK: movsbl ({{.*}},4), %eax
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; ATOM: test4:
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; ATOM: movsbl ({{.*}},4), %eax
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}
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define void @test5(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) nounwind {
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%x = select i1 %c, <2 x i16> %a, <2 x i16> %b
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store <2 x i16> %x, <2 x i16>* %p
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ret void
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; CHECK: test5:
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; ATOM: test5:
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}
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define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind {
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%tmp = load <4 x float>* %A ; <<4 x float>> [#uses=1]
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%tmp3 = load <4 x float>* %B ; <<4 x float>> [#uses=2]
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%tmp9 = fmul <4 x float> %tmp3, %tmp3 ; <<4 x float>> [#uses=1]
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%tmp.upgrd.1 = icmp eq i32 %C, 0 ; <i1> [#uses=1]
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%iftmp.38.0 = select i1 %tmp.upgrd.1, <4 x float> %tmp9, <4 x float> %tmp ; <<4 x float>> [#uses=1]
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store <4 x float> %iftmp.38.0, <4 x float>* %A
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ret void
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; Verify that the fmul gets sunk into the one part of the diamond where it is
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; needed.
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; CHECK: test6:
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; CHECK: je
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; CHECK: ret
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; CHECK: mulps
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; CHECK: ret
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; ATOM: test6:
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; ATOM: je
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; ATOM: ret
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; ATOM: mulps
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; ATOM: ret
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}
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; Select with fp80's
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define x86_fp80 @test7(i32 %tmp8) nounwind {
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%tmp9 = icmp sgt i32 %tmp8, -1 ; <i1> [#uses=1]
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%retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000
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ret x86_fp80 %retval
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; CHECK: test7:
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; CHECK: leaq
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; CHECK: fldt (%r{{.}}x,%r{{.}}x)
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; ATOM: test7:
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; ATOM: leaq
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; ATOM: fldt (%r{{.}}x,%r{{.}}x)
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}
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; widening select v6i32 and then a sub
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define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwind {
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%x = select i1 %c, <6 x i32> %src1, <6 x i32> %src2
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%val = sub <6 x i32> %x, < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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store <6 x i32> %val, <6 x i32>* %dst.addr
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ret void
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; CHECK: test8:
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; ATOM: test8:
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}
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;; Test integer select between values and constants.
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define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp ne i64 %x, 0
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%cond = select i1 %cmp, i64 %y, i64 -1
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ret i64 %cond
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; CHECK: test9:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: orq %rsi, %rax
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; CHECK: ret
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; ATOM: test9:
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; ATOM: cmpq $1, %rdi
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; ATOM: sbbq %rax, %rax
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; ATOM: orq %rsi, %rax
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; ATOM: ret
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}
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;; Same as test9
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define i64 @test9a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp eq i64 %x, 0
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%cond = select i1 %cmp, i64 -1, i64 %y
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ret i64 %cond
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; CHECK: test9a:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: orq %rsi, %rax
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; CHECK: ret
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; ATOM: test9a:
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; ATOM: cmpq $1, %rdi
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; ATOM: sbbq %rax, %rax
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; ATOM: orq %rsi, %rax
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; ATOM: ret
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}
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define i64 @test9b(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp eq i64 %x, 0
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%A = sext i1 %cmp to i64
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%cond = or i64 %y, %A
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ret i64 %cond
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; CHECK: test9b:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: orq %rsi, %rax
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; CHECK: ret
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; ATOM: test9b:
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; ATOM: cmpq $1, %rdi
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; ATOM: sbbq %rax, %rax
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; ATOM: orq %rsi, %rax
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; ATOM: ret
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}
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;; Select between -1 and 1.
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define i64 @test10(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp eq i64 %x, 0
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%cond = select i1 %cmp, i64 -1, i64 1
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ret i64 %cond
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; CHECK: test10:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: orq $1, %rax
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; CHECK: ret
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; ATOM: test10:
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; ATOM: cmpq $1, %rdi
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; ATOM: sbbq %rax, %rax
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; ATOM: orq $1, %rax
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; ATOM: ret
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}
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define i64 @test11(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp eq i64 %x, 0
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%cond = select i1 %cmp, i64 %y, i64 -1
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ret i64 %cond
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; CHECK: test11:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: notq %rax
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; CHECK: orq %rsi, %rax
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; CHECK: ret
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; ATOM: test11:
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; ATOM: cmpq $1, %rdi
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; ATOM: sbbq %rax, %rax
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; ATOM: notq %rax
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; ATOM: orq %rsi, %rax
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; ATOM: ret
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}
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define i64 @test11a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp ne i64 %x, 0
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%cond = select i1 %cmp, i64 -1, i64 %y
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ret i64 %cond
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; CHECK: test11a:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: notq %rax
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; CHECK: orq %rsi, %rax
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; CHECK: ret
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; ATOM: test11a:
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; ATOM: cmpq $1, %rdi
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; ATOM: sbbq %rax, %rax
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; ATOM: notq %rax
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; ATOM: orq %rsi, %rax
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; ATOM: ret
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}
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declare noalias i8* @_Znam(i64) noredzone
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define noalias i8* @test12(i64 %count) nounwind ssp noredzone {
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entry:
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%A = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %count, i64 4)
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%B = extractvalue { i64, i1 } %A, 1
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%C = extractvalue { i64, i1 } %A, 0
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%D = select i1 %B, i64 -1, i64 %C
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%call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone
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ret i8* %call
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; CHECK: test12:
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; CHECK: movq $-1, %rdi
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; CHECK: mulq
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; CHECK: cmovnoq %rax, %rdi
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; CHECK: jmp __Znam
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; ATOM: test12:
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; ATOM: mulq
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; ATOM: movq $-1, %rdi
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; ATOM: cmovnoq %rax, %rdi
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; ATOM: jmp __Znam
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}
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declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
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define i32 @test13(i32 %a, i32 %b) nounwind {
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%c = icmp ult i32 %a, %b
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%d = sext i1 %c to i32
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ret i32 %d
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; CHECK: test13:
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; CHECK: cmpl
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; CHECK-NEXT: sbbl
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; CHECK-NEXT: ret
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; ATOM: test13:
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; ATOM: cmpl
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; ATOM-NEXT: sbbl
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; ATOM: ret
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}
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define i32 @test14(i32 %a, i32 %b) nounwind {
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%c = icmp uge i32 %a, %b
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%d = sext i1 %c to i32
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ret i32 %d
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; CHECK: test14:
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; CHECK: cmpl
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; CHECK-NEXT: sbbl
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; CHECK-NEXT: notl
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; CHECK-NEXT: ret
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; ATOM: test14:
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; ATOM: cmpl
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; ATOM-NEXT: sbbl
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; ATOM-NEXT: notl
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; ATOM: ret
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}
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; rdar://10961709
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define i32 @test15(i32 %x) nounwind {
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entry:
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%cmp = icmp ne i32 %x, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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; CHECK: test15:
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; CHECK: negl
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; CHECK: sbbl
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; ATOM: test15:
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; ATOM: negl
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; ATOM: sbbl
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}
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define i64 @test16(i64 %x) nounwind uwtable readnone ssp {
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entry:
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%cmp = icmp ne i64 %x, 0
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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; CHECK: test16:
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; CHECK: negq
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; CHECK: sbbq
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; ATOM: test16:
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; ATOM: negq
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; ATOM: sbbq
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}
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define i16 @test17(i16 %x) nounwind {
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entry:
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%cmp = icmp ne i16 %x, 0
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%sub = sext i1 %cmp to i16
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ret i16 %sub
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; CHECK: test17:
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; CHECK: negw
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; CHECK: sbbw
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; ATOM: test17:
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; ATOM: negw
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; ATOM: sbbw
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}
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define i8 @test18(i32 %x, i8 zeroext %a, i8 zeroext %b) nounwind {
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%cmp = icmp slt i32 %x, 15
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%sel = select i1 %cmp, i8 %a, i8 %b
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ret i8 %sel
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; CHECK: test18:
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; CHECK: cmpl $15, %edi
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; CHECK: cmovgel %edx
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; ATOM: test18:
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; ATOM: cmpl $15, %edi
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; ATOM: cmovgel %edx
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}
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