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d4d961615c
when run on an Intel Atom processor. The failures have arisen due to changes elsewhere in the trunk over the past 8 weeks or so. These failures were not detected by the Atom buildbot because the CPU on the Atom buildbot was not being detected as an Atom CPU. The fix for this problem is in Host.cpp and X86Subtarget.cpp, but shall remain commented out until the current set of Atom test failures are fixed. Patch by Andy Zhang and Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160451 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.4 KiB
LLVM
48 lines
1.4 KiB
LLVM
; RUN: llc -march=x86 -mcpu=generic -mattr=+sse < %s | FileCheck %s
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; RUN: llc -march=x86 -mcpu=atom -mattr=+sse < %s | FileCheck -check-prefix=ATOM %s
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%vec = type <6 x float>
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; CHECK: divss
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; CHECK: divss
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; CHECK: divps
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; Scheduler causes a different instruction order to be produced on Intel Atom
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; ATOM: divps
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; ATOM: divss
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; ATOM: divss
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define %vec @vecdiv( %vec %p1, %vec %p2)
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{
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%result = fdiv %vec %p1, %p2
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ret %vec %result
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}
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@a = constant %vec < float 2.0, float 4.0, float 8.0, float 16.0, float 32.0, float 64.0 >
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@b = constant %vec < float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0 >
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; Expected result: < 1.0, 2.0, 4.0, ..., 2.0^(n-1) >
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; main() returns 0 if the result is expected and 1 otherwise
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; to execute, use llvm-as < %s | lli
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define i32 @main() nounwind {
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entry:
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%avec = load %vec* @a
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%bvec = load %vec* @b
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%res = call %vec @vecdiv(%vec %avec, %vec %bvec)
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br label %loop
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loop:
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%idx = phi i32 [0, %entry], [%nextInd, %looptail]
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%expected = phi float [1.0, %entry], [%nextExpected, %looptail]
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%elem = extractelement %vec %res, i32 %idx
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%expcmp = fcmp oeq float %elem, %expected
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br i1 %expcmp, label %looptail, label %return
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looptail:
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%nextExpected = fmul float %expected, 2.0
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%nextInd = add i32 %idx, 1
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%cmp = icmp slt i32 %nextInd, 6
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br i1 %cmp, label %loop, label %return
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return:
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%retval = phi i32 [0, %looptail], [1, %loop]
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ret i32 %retval
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}
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